diff mbox series

[v2,01/10] common/cnxk: fix shift offset for TL3 length disable

Message ID 20220121120424.28166-1-ndabilpuram@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series [v2,01/10] common/cnxk: fix shift offset for TL3 length disable |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Jan. 21, 2022, 12:04 p.m. UTC 
  Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE
register to be 24 instead of zero similar to other level SHAPE
registers. Also mask unused bits in adjust value.

Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---

v2:
- Updated series from Jerin
- Handle comments from Ferruh in patch 3/8.
- Split patch 6/8 to two patches 
- Split patch 7/8 to two patches

 drivers/common/cnxk/roc_nix_tm_utils.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 543adf9..9e80c2a 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -642,6 +642,7 @@  nix_tm_shaper_reg_prep(struct nix_tm_node *node,
 	else if (profile)
 		adjust = profile->pkt_len_adj;
 
+	adjust &= 0x1FF;
 	plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, "
 		   "pir %" PRIu64 "(%" PRIu64 "B),"
 		   " cir %" PRIu64 "(%" PRIu64 "B)"
@@ -708,7 +709,7 @@  nix_tm_shaper_reg_prep(struct nix_tm_node *node,
 		/* Configure RED algo */
 		reg[k] = NIX_AF_TL3X_SHAPE(schq);
 		regval[k] = (adjust | (uint64_t)node->red_algo << 9 |
-			     (uint64_t)node->pkt_mode);
+			     (uint64_t)node->pkt_mode << 24);
 		k++;
 
 		break;