From patchwork Mon Jan 24 05:18:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 106324 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F01B5A04A6; Mon, 24 Jan 2022 06:35:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 60949427B9; Mon, 24 Jan 2022 06:35:35 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 0A87340040; Mon, 24 Jan 2022 06:35:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643002534; x=1674538534; h=from:to:cc:subject:date:message-id; bh=3PzofJwNTAZnlBwBY1an++cvZuuCeXFc+5uEhZvqIUM=; b=LpdKKBbFOzx5aTv7qjklwjARaNLCaX3N84XivtwArrs7pJBx8yOmtYgj +P5m/VAHiY7XAdLrpjNqubSf1p8Rcc/6756E2oY5OgiASpw64e9qWfbDN D9RrKPMW6yhEywMFJ9nfAylLmoNqcEyL/JeV0nXL8jb6p4AAbEJ7QIocd HvXVQ83ew9Es/Ew45uVr0bWTtqDN0iqaktBKXwrR7Xqi+13I0Muz1Lvxw iVvAQ+INrfkLfmNV8QCXeSDVTrYGKoCE3vOpi4A8i3JM2Z4JlflOk8cN6 yBGsTiHvjPRJjTgTpBjibGNN5WosTfirk0QWqMiJQJ7g5RwW7A4AZalOn g==; X-IronPort-AV: E=McAfee;i="6200,9189,10236"; a="226641072" X-IronPort-AV: E=Sophos;i="5.88,311,1635231600"; d="scan'208";a="226641072" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2022 21:35:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,311,1635231600"; d="scan'208";a="627365779" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.218]) by orsmga004.jf.intel.com with ESMTP; 23 Jan 2022 21:35:31 -0800 From: Simei Su To: qi.z.zhang@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, Simei Su , stable@dpdk.org Subject: [PATCH] net/ice: fix incorrect Rx timestamp in Windows PTP Date: Mon, 24 Jan 2022 13:18:23 +0800 Message-Id: <20220124051823.32879-1-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rx PHY timer init value is not same as primary timer init value when power up which will lead Rx timestamp always have big gap compared with PTP timestamp. This patch adds PHC init time in initializing PTP hardware clock. Fixes: 646dcbe6c701 ("net/ice: support IEEE 1588 PTP") Cc: stable@dpdk.org Signed-off-by: Simei Su --- drivers/net/ice/ice_ethdev.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 13a7a97..d57355d 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -5501,6 +5501,8 @@ ice_timesync_enable(struct rte_eth_dev *dev) struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ice_adapter *ad = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + uint64_t start_time; + struct timespec system_time; int ret; if (dev->data->dev_started && !(dev->data->dev_conf.rxmode.offloads & @@ -5522,6 +5524,15 @@ ice_timesync_enable(struct rte_eth_dev *dev) "Failed to write PHC increment time value"); return -1; } + + clock_gettime(CLOCK_MONOTONIC, &system_time); + start_time = system_time.tv_sec * NSEC_PER_SEC + + system_time.tv_nsec; + ret = ice_ptp_init_time(hw, start_time); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to write PHC initial time"); + return -1; + } } /* Initialize cycle counters for system time/RX/TX timestamp */