From patchwork Mon Feb 14 09:35:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 107436 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F02EBA00C4; Mon, 14 Feb 2022 10:37:08 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB9FB41C3B; Mon, 14 Feb 2022 10:36:01 +0100 (CET) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2071.outbound.protection.outlook.com [40.107.93.71]) by mails.dpdk.org (Postfix) with ESMTP id 7645341C3B for ; Mon, 14 Feb 2022 10:36:00 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EGTNMloZhyicSWOCmmETlBhl7KJPcjWoumFz++p9RK+Z4ku1XZlTE4JlLjO7VFivjxeh8+XkHwYe8Dp31HQvods8yxGmDf8lPduenk60+zZzTuhaH1jZ7qvuK7DdDNVpvdqJOPUV4Krf45lc1y+gpB5n5EbLnet99qmfREeBsCyLDxnRtGYP8XhYo8XjkgNrZl3T3abM04DGOsDJrclnwIEdfMllJfz/UiDi9R+erwWCd+r/QIY/ya8ylLXpm+jYKXIE9xWtgrtfIdEU3ehE+T9t9KIgCNW4PQxpfnoIpvVN61BjoTd/ctQYxV8LmSc0pTkgs3c1sdhfYQx17omkBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2b4C1jZN/ouX43+9YqjoieK8If8M0RyjWtlcVN2OvNE=; b=NGkhAA0SuB+7AAzoeNQ5qsZtmUEfiPaSF1S81N8ySqc6q5KVItCIU2UDIfkj9JYAEfYlb30o8um/566V0bXl7xf0yvuWkihBlUqA+5eFRCJvVuQIYlNyvDgBYUDogqFSTYR7M/B6yuUB+V0pG8JfNj8ObXJjk8VMZmqCZFwLctL9iJoFUpKxI/iwcMHxYG604h7L7HmzhZezok23SH1kGjjnGOcXxMoiRSRwQqHCpoS2/jjzmayNe7w96NnBhLZyN6MWmZIrhHyUQjLO4r7wVarZIoSo1xFTPfaBfEoYraL5tNL+zPP8N+xIvTAz0yzJ4RBevCP/wqqEeF4+/BHqDQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2b4C1jZN/ouX43+9YqjoieK8If8M0RyjWtlcVN2OvNE=; b=TRJVYI+pYeFe+Hi2alzIAiZ/M9TCA9HkgSbhwk60m73+GXrwlMi/AJG623ZXVGjjsPiYoRYVdGVgB21kUy1CxlXUcAo9qWxk6mmEMUFhrsosvsuvK478O7H5sP459DcR8AXorsHoV9of1hRP+RD1DMkzUDsFXRhBi7IhZDX77KVq+30+tMI4OsD0vHHDu6OeZYWx0ZNjVDeSi0tgzFa9ZxxFnODRbWkH2owkLkMqcXQ9QlBnE6NAayh6FdA9+YjeO4xW3bxYTWzFAoK9DLwb+MVY8pc6M4yIkni12lq9NA2AS6Oy5Dp5TiwVorHqbsSgj9KpQfSe/HfnOFlihDVfDA== Received: from DM6PR03CA0023.namprd03.prod.outlook.com (2603:10b6:5:40::36) by MN2PR12MB4174.namprd12.prod.outlook.com (2603:10b6:208:15f::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.15; Mon, 14 Feb 2022 09:35:58 +0000 Received: from DM6NAM11FT003.eop-nam11.prod.protection.outlook.com (2603:10b6:5:40:cafe::52) by DM6PR03CA0023.outlook.office365.com (2603:10b6:5:40::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.12 via Frontend Transport; Mon, 14 Feb 2022 09:35:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT003.mail.protection.outlook.com (10.13.173.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4975.11 via Frontend Transport; Mon, 14 Feb 2022 09:35:58 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 14 Feb 2022 09:35:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Mon, 14 Feb 2022 01:35:57 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend Transport; Mon, 14 Feb 2022 01:35:55 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH v2 17/20] net/mlx5: using function to detect operation by DevX Date: Mon, 14 Feb 2022 11:35:08 +0200 Message-ID: <20220214093511.1592698-18-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214093511.1592698-1-michaelba@nvidia.com> References: <20220127153950.812953-1-michaelba@nvidia.com> <20220214093511.1592698-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e85373a5-92cf-4fe1-23c6-08d9ef9d6822 X-MS-TrafficTypeDiagnostic: MN2PR12MB4174:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F4ivbB81XsLQCuyI53sGzCslZjb9120fM2NXaANg9FJ/Ry/Ti/4zcOlxtJ6p+rv6NK9y3HdYKMd5oeo0Oxb4Xm5NBC0b9NglICE75JoeNbssqpI8DWM7SxhZw2Bk0895khdP1cyLUdWjNYkEXSqqSL3BRGmwbjLaiE0A9pef9+LyOTX+JUcXcZkT4/sM8GWKSJ/iy/w4rsRWzWb4HA0bMOAwL27dHpZjuxX+EaWUo0APJUQTcuVL45D9cipTEnzX2atHjNmOKUBDrkbbVsrXtWFlb7CjxfLVOf+6HOOfSAPlkvizIukh64ewl4HPcsynjkL679wn0coP20qBYjj1SAW5VKdPwMqHe47JF36uSzJJYMzWk1E5MDyLddzk8rMa3goelpv+8m+gPqDo/CcYGklWHB8Akr1bsFubpAiF1kocrlXWZwbRFpKkULSUCcU7KY3t6qcYS6sgX0Ji915+H4YJxlsOUV6ar7KGroO7X0IcAcRasH5SK7vyVVGMGBcNPyq/iKQVuawx1ajTMws13hBO+lG7CZV1LDa31eqEXku5iRqMgpDXsJfYwNQLzbWULWqrVD/WDpK0ksiJSDplDasslpQ+/nd/4ZBkUN7ChbdmwG101BEJiAWJv9l6byaJN0Ws8VoOE6cuPKghMndF1YmVCk/rLoWctb8YLuvJ8ZWs0tykyun1EUsGqa5nOJNJgcy/tNHAAwJvkm1WOpVT/g== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(6916009)(107886003)(54906003)(186003)(7696005)(316002)(26005)(6286002)(55016003)(5660300002)(47076005)(2616005)(336012)(1076003)(81166007)(82310400004)(70206006)(2906002)(8936002)(8676002)(86362001)(36860700001)(36756003)(6666004)(70586007)(4326008)(356005)(83380400001)(508600001)(40460700003)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 09:35:58.3576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e85373a5-92cf-4fe1-23c6-08d9ef9d6822 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4174 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add inline function indicating whether HW objects operations can be created by DevX. It makes the code more readable. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 6 ++---- drivers/net/mlx5/mlx5.h | 24 ++++++++++++++++++++++++ drivers/net/mlx5/mlx5_ethdev.c | 3 +-- drivers/net/mlx5/mlx5_trigger.c | 3 +-- 4 files changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 7ee76d54bd..c1eda00899 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -370,8 +370,7 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) sh->dev_cap.txpp_en = 0; #endif /* Check for LRO support. */ - if (sh->dev_cap.dest_tir && sh->dev_cap.dv_flow_en && - hca_attr->lro_cap) { + if (mlx5_devx_obj_ops_en(sh) && hca_attr->lro_cap) { /* TBD check tunnel lro caps. */ sh->dev_cap.lro_supported = 1; DRV_LOG(DEBUG, "Device supports LRO."); @@ -1550,8 +1549,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, if (mlx5_flex_item_port_init(eth_dev) < 0) goto error; } - if (sh->cdev->config.devx && sh->config.dv_flow_en && - sh->dev_cap.dest_tir) { + if (mlx5_devx_obj_ops_en(sh)) { priv->obj_ops = devx_obj_ops; mlx5_queue_counter_id_prepare(eth_dev); priv->obj_ops.lb_dummy_queue_create = diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 5ca48ef68f..46fa5131a7 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1496,6 +1496,30 @@ enum dr_dump_rec_type { DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, }; +/** + * Indicates whether HW objects operations can be created by DevX. + * + * This function is used for both: + * Before creation - deciding whether to create HW objects operations by DevX. + * After creation - indicator if HW objects operations were created by DevX. + * + * @param sh + * Pointer to shared device context. + * + * @return + * True if HW objects were created by DevX, False otherwise. + */ +static inline bool +mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh) +{ + /* + * When advanced DR API is available and DV flow is supported and + * DevX is supported, HW objects operations are created by DevX. + */ + return (sh->cdev->config.devx && sh->config.dv_flow_en && + sh->dev_cap.dest_tir); +} + /* mlx5.c */ int mlx5_getenv_int(const char *); diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 9e478db8df..d637dee98d 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -721,8 +721,7 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) { struct mlx5_priv *priv = dev->data->dev_private; - if (!priv->sh->cdev->config.devx || !priv->sh->dev_cap.dest_tir || - !priv->sh->config.dv_flow_en) { + if (!mlx5_devx_obj_ops_en(priv->sh)) { rte_errno = ENOTSUP; return -rte_errno; } diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index a67a6af728..74c3bc8a13 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1104,8 +1104,7 @@ mlx5_dev_start(struct rte_eth_dev *dev) dev->data->port_id, strerror(rte_errno)); goto error; } - if ((priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en && - priv->sh->dev_cap.dest_tir) && + if (mlx5_devx_obj_ops_en(priv->sh) && priv->obj_ops.lb_dummy_queue_create) { ret = priv->obj_ops.lb_dummy_queue_create(dev); if (ret)