@@ -653,6 +653,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
void *hcattr;
int status, syndrome, rc, i;
+ bool hca_cap_2_sup;
MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
MLX5_SET(query_hca_cap_in, in, op_mod,
@@ -672,6 +673,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
return -1;
}
hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
+ hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
attr->flow_counter_bulk_alloc_bitmap =
MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
@@ -733,6 +735,32 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
mini_cqe_resp_flow_tag);
attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
mini_cqe_resp_l3_l4_tag);
+ if (hca_cap_2_sup) {
+ memset(in, 0, sizeof(in));
+ memset(out, 0, sizeof(out));
+ MLX5_SET(query_hca_cap_in, in, opcode,
+ MLX5_CMD_OP_QUERY_HCA_CAP);
+ MLX5_SET(query_hca_cap_in, in, op_mod,
+ MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
+ out, sizeof(out));
+ if (rc)
+ goto error;
+ status = MLX5_GET(query_hca_cap_out, out, status);
+ syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
+ if (status) {
+ DRV_LOG(DEBUG,
+ "Failed to query DevX HCA capabilities 2,"
+ " status %x, syndrome = %x", status, syndrome);
+ return -1;
+ }
+ hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
+ attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
+ log_min_stride_wqe_sz);
+ }
+ if (attr->log_min_stride_wqe_sz == 0)
+ attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
if (attr->qos.sup) {
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
@@ -79,6 +79,7 @@ struct mlx5_hca_attr {
uint32_t eswitch_manager:1;
uint32_t flow_counters_dump:1;
uint32_t log_max_rqt_size:5;
+ uint32_t log_min_stride_wqe_sz:5;
uint32_t parse_graph_flex_node:1;
uint8_t flow_counter_bulk_alloc_bitmap;
uint32_t eth_net_offloads:1;
@@ -264,6 +264,9 @@
/* The maximum log value of segments per RQ WQE. */
#define MLX5_MAX_LOG_RQ_SEGS 5u
+/* Log 2 of the default size of a WQE for Multi-Packet RQ. */
+#define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U
+
/* The alignment needed for WQ buffer. */
#define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
@@ -1059,6 +1062,7 @@ enum {
MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
+ MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
};
#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
@@ -1119,7 +1123,9 @@ enum {
#define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
struct mlx5_ifc_cmd_hca_cap_bits {
- u8 reserved_at_0[0x30];
+ u8 reserved_at_0[0x20];
+ u8 hca_cap_2[0x1];
+ u8 reserved_at_21[0xf];
u8 vhca_id[0x10];
u8 reserved_at_40[0x40];
u8 log_max_srq_sz[0x8];
@@ -1572,8 +1578,38 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
};
+/*
+ * HCA Capabilities 2
+ */
+struct mlx5_ifc_cmd_hca_cap_2_bits {
+ u8 reserved_at_0[0x80]; /* End of DW4. */
+ u8 reserved_at_80[0x3];
+ u8 max_num_prog_sample_field[0x5];
+ u8 reserved_at_88[0x3];
+ u8 log_max_num_reserved_qpn[0x5];
+ u8 reserved_at_90[0x3];
+ u8 log_reserved_qpn_granularity[0x5];
+ u8 reserved_at_98[0x3];
+ u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
+ u8 max_reformat_insert_size[0x8];
+ u8 max_reformat_insert_offset[0x8];
+ u8 max_reformat_remove_size[0x8];
+ u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
+ u8 reserved_at_c0[0x3];
+ u8 log_min_stride_wqe_sz[0x5];
+ u8 reserved_at_c8[0x3];
+ u8 log_conn_track_granularity[0x5];
+ u8 reserved_at_d0[0x3];
+ u8 log_conn_track_max_alloc[0x5];
+ u8 reserved_at_d8[0x3];
+ u8 log_max_conn_track_offload[0x5];
+ u8 reserved_at_e0[0x20]; /* End of DW7. */
+ u8 reserved_at_100[0x700];
+};
+
union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
+ struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
struct mlx5_ifc_per_protocol_networking_offload_caps_bits
per_protocol_networking_offload_caps;
struct mlx5_ifc_qos_cap_bits qos_cap;