From patchwork Tue Feb 22 19:34:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 108055 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A0FFA034C; Tue, 22 Feb 2022 20:35:46 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E696F4115B; Tue, 22 Feb 2022 20:35:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D6A8841143 for ; Tue, 22 Feb 2022 20:35:31 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21MIlBms020298; Tue, 22 Feb 2022 11:35:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=vFp+H0eCkdFkWZh6FP3N0uKtnj5/cm4ja+TgUZNxPMs=; b=H6YWbIZacpxmEkdS4sLEwQFJR2HOkLRC5cSCeKGZq+s3jKdUhOu06hnV+hwAsL8zB9ul JNXcr3Kflq43pM5G2JHWfuz1eQ/uVYn27CFnX+Aaf+ajuWoHtEOTYVn/GVdNCGopLRiL gHQS+EkuYmNIRMCToECCyFMo+OnVYPE36a8Zo5U4RouzeMtZ+w/HqhTAxmVJeR617zra cR04ifubWEY3PVzxfgAgA9nzWv174ipDwCdvbn5rjcUb7QzaScngpNj/QeMOs9k1SlJH AwzfjBuQ8RQlj/5t0s3+8965A8ElvggeS7ohhGfazLYWveK/Muo3sl6jkIVqJr/hR2Wp kA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ecwaxar1g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 22 Feb 2022 11:35:28 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Feb 2022 11:35:27 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Feb 2022 11:35:26 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 882E73F707B; Tue, 22 Feb 2022 11:35:24 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Vidya Sagar Velumuri Subject: [PATCH v2 04/21] common/cnxk: support inline device API without ROC NIX Date: Wed, 23 Feb 2022 01:04:55 +0530 Message-ID: <20220222193512.19292-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220222193512.19292-1-ndabilpuram@marvell.com> References: <20220207072932.22409-1-ndabilpuram@marvell.com> <20220222193512.19292-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: E9OU2MZa5ZL4f4_6AD3BKEF3xh6DeZZH X-Proofpoint-ORIG-GUID: E9OU2MZa5ZL4f4_6AD3BKEF3xh6DeZZH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-22_06,2022-02-21_02,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Update the inline device functions to work when roc_nix is NULL. This is required, as IPsec driver have to use these APIs to work with inline IPsec device, but the IPsec driver might not have roc_nix information. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_nix_inl.c | 98 ++++++++++++++++++++++++---------- drivers/common/cnxk/roc_nix_inl.h | 2 + drivers/common/cnxk/roc_nix_inl_dev.c | 7 +++ drivers/common/cnxk/roc_nix_inl_priv.h | 1 + drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev_sec.c | 2 + 6 files changed, 84 insertions(+), 27 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index e8981c4..356d11d 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -107,18 +107,24 @@ roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix) uintptr_t roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev) { - struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct idev_cfg *idev = idev_get_cfg(); struct nix_inl_dev *inl_dev; + struct nix *nix = NULL; if (idev == NULL) return 0; - if (!nix->inl_inb_ena) - return 0; + if (!inb_inl_dev && roc_nix == NULL) + return -EINVAL; + + if (roc_nix) { + nix = roc_nix_to_nix_priv(roc_nix); + if (!nix->inl_inb_ena) + return 0; + } - inl_dev = idev->nix_inl_dev; if (inb_inl_dev) { + inl_dev = idev->nix_inl_dev; /* Return inline dev sa base */ if (inl_dev) return (uintptr_t)inl_dev->inb_sa_base; @@ -131,18 +137,24 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev) uint32_t roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev) { - struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct idev_cfg *idev = idev_get_cfg(); struct nix_inl_dev *inl_dev; + struct nix *nix; if (idev == NULL) return 0; - if (!nix->inl_inb_ena) - return 0; + if (!inb_inl_dev && roc_nix == NULL) + return -EINVAL; + + if (roc_nix) { + nix = roc_nix_to_nix_priv(roc_nix); + if (!nix->inl_inb_ena) + return 0; + } - inl_dev = idev->nix_inl_dev; if (inb_inl_dev) { + inl_dev = idev->nix_inl_dev; if (inl_dev) return inl_dev->ipsec_in_max_spi; return 0; @@ -154,21 +166,28 @@ roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev) uint32_t roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa) { - struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct idev_cfg *idev = idev_get_cfg(); struct nix_inl_dev *inl_dev; + struct nix *nix; if (idev == NULL) return 0; - if (!inl_dev_sa) - return nix->inb_sa_sz; + if (!inl_dev_sa && roc_nix == NULL) + return -EINVAL; - inl_dev = idev->nix_inl_dev; - if (inl_dev_sa && inl_dev) - return inl_dev->inb_sa_sz; + if (roc_nix) { + nix = roc_nix_to_nix_priv(roc_nix); + if (!inl_dev_sa) + return nix->inb_sa_sz; + } + + if (inl_dev_sa) { + inl_dev = idev->nix_inl_dev; + if (inl_dev) + return inl_dev->inb_sa_sz; + } - /* On error */ return 0; } @@ -536,7 +555,7 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq) inl_rq->tag_mask = 0xFFF00000; inl_rq->tt = SSO_TT_ORDERED; inl_rq->hwgrp = 0; - inl_rq->wqe_skip = 1; + inl_rq->wqe_skip = inl_dev->wqe_skip; inl_rq->sso_ena = true; /* Prepare and send RQ init mbox */ @@ -731,13 +750,14 @@ int roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, enum roc_nix_inl_sa_sync_op op) { - struct nix *nix = roc_nix_to_nix_priv(roc_nix); - struct roc_cpt_lf *outb_lf = nix->cpt_lf_base; struct idev_cfg *idev = idev_get_cfg(); struct nix_inl_dev *inl_dev = NULL; + struct roc_cpt_lf *outb_lf = NULL; union cpt_lf_ctx_reload reload; union cpt_lf_ctx_flush flush; + bool get_inl_lf = true; uintptr_t rbase; + struct nix *nix; /* Nothing much to do on cn9k */ if (roc_model_is_cn9k()) { @@ -745,11 +765,22 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, return 0; } - if (inb && nix->inb_inl_dev) { + if (idev) + inl_dev = idev->nix_inl_dev; + + if (!inl_dev && roc_nix == NULL) + return -EINVAL; + + if (roc_nix) { + nix = roc_nix_to_nix_priv(roc_nix); + outb_lf = nix->cpt_lf_base; + if (inb && !nix->inb_inl_dev) + get_inl_lf = false; + } + + if (inb && get_inl_lf) { outb_lf = NULL; - if (idev) - inl_dev = idev->nix_inl_dev; - if (inl_dev) + if (inl_dev && inl_dev->attach_cptlf) outb_lf = &inl_dev->cpt_lf; } @@ -783,12 +814,13 @@ int roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, bool inb, uint16_t sa_len) { - struct nix *nix = roc_nix_to_nix_priv(roc_nix); - struct roc_cpt_lf *outb_lf = nix->cpt_lf_base; struct idev_cfg *idev = idev_get_cfg(); struct nix_inl_dev *inl_dev = NULL; + struct roc_cpt_lf *outb_lf = NULL; union cpt_lf_ctx_flush flush; + bool get_inl_lf = true; uintptr_t rbase; + struct nix *nix; int rc; /* Nothing much to do on cn9k */ @@ -797,10 +829,22 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, return 0; } - if (inb && nix->inb_inl_dev) { + if (idev) + inl_dev = idev->nix_inl_dev; + + if (!inl_dev && roc_nix == NULL) + return -EINVAL; + + if (roc_nix) { + nix = roc_nix_to_nix_priv(roc_nix); + outb_lf = nix->cpt_lf_base; + + if (inb && !nix->inb_inl_dev) + get_inl_lf = false; + } + + if (inb && get_inl_lf) { outb_lf = NULL; - if (idev) - inl_dev = idev->nix_inl_dev; if (inl_dev && inl_dev->attach_cptlf) outb_lf = &inl_dev->cpt_lf; } diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index bbdcbc8..ceeccab 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -111,6 +111,7 @@ struct roc_nix_inl_dev { uint16_t channel; uint16_t chan_mask; bool attach_cptlf; + bool wqe_skip; /* End of input parameters */ #define ROC_NIX_INL_MEM_SZ (1280) @@ -125,6 +126,7 @@ bool __roc_api roc_nix_inl_dev_is_probed(void); void __roc_api roc_nix_inl_dev_lock(void); void __roc_api roc_nix_inl_dev_unlock(void); int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle); +uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void); /* NIX Inline Inbound API */ int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 1d14f04..12160e9 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -27,6 +27,12 @@ nix_inl_dev_pffunc_get(void) return 0; } +uint16_t +roc_nix_inl_dev_pffunc_get(void) +{ + return nix_inl_dev_pffunc_get(); +} + static void nix_inl_selftest_work_cb(uint64_t *gw, void *args) { @@ -655,6 +661,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->channel = roc_inl_dev->channel; inl_dev->chan_mask = roc_inl_dev->chan_mask; inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf; + inl_dev->wqe_skip = roc_inl_dev->wqe_skip; /* Initialize base device */ rc = dev_init(&inl_dev->dev, pci_dev); diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index 17df23f..dcf752e 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -58,6 +58,7 @@ struct nix_inl_dev { bool is_multi_channel; uint16_t ipsec_in_max_spi; bool attach_cptlf; + bool wqe_skip; }; int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index ff3c1e8..464df44 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -157,6 +157,7 @@ INTERNAL { roc_nix_inl_outb_is_enabled; roc_nix_inl_sa_sync; roc_nix_inl_ctx_write; + roc_nix_inl_dev_pffunc_get; roc_nix_inl_inb_sa_init; roc_nix_inl_outb_sa_init; roc_nix_cpt_ctx_cache_sync; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 3fef056..ea204ca 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -278,6 +278,8 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, } inl_dev->attach_cptlf = true; + /* WQE skip is one for DPDK */ + inl_dev->wqe_skip = true; rc = roc_nix_inl_dev_init(inl_dev); if (rc) { plt_err("Failed to init nix inl device, rc=%d(%s)", rc,