diff mbox series

common/mlx5: fix MR range calculation

Message ID 20220331143316.3343802-1-dkozlyuk@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series common/mlx5: fix MR range calculation |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/github-robot: build success github build: passed
ci/iol-abi-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS

Commit Message

Dmitry Kozlyuk March 31, 2022, 2:33 p.m. UTC 
  MR end for a mempool chunk may be calculated incorrectly.
For example, for chunk with addr=1.5M and len=1M with 2M page size
the range would be [0, 2M), while the proper result is [0, 4M).
Fix the calculation.

Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities")
Cc: stable@dpdk.org

Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_common_mr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Raslan Darawsheh April 12, 2022, 8:08 a.m. UTC | #1 
Hi,

> -----Original Message-----
> From: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
> Sent: Thursday, March 31, 2022 5:33 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>
> Subject: [PATCH] common/mlx5: fix MR range calculation
> 
> MR end for a mempool chunk may be calculated incorrectly.
> For example, for chunk with addr=1.5M and len=1M with 2M page size the
> range would be [0, 2M), while the proper result is [0, 4M).
> Fix the calculation.
> 
> Fixes: 690b2a88c2f7 ("common/mlx5: add mempool registration facilities")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c
index fa27bd98de..06e4c8f187 100644
--- a/drivers/common/mlx5/mlx5_common_mr.c
+++ b/drivers/common/mlx5/mlx5_common_mr.c
@@ -1289,11 +1289,12 @@  mlx5_range_from_mempool_chunk(struct rte_mempool *mp, void *opaque,
 			      unsigned int idx)
 {
 	struct mlx5_range *ranges = opaque, *range = &ranges[idx];
+	uintptr_t start = (uintptr_t)memhdr->addr;
 	uint64_t page_size = rte_mem_page_size();
 
 	RTE_SET_USED(mp);
-	range->start = RTE_ALIGN_FLOOR((uintptr_t)memhdr->addr, page_size);
-	range->end = RTE_ALIGN_CEIL(range->start + memhdr->len, page_size);
+	range->start = RTE_ALIGN_FLOOR(start, page_size);
+	range->end = RTE_ALIGN_CEIL(start + memhdr->len, page_size);
 }
 
 /**