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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT040.mail.protection.outlook.com (10.13.173.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Fri, 1 Apr 2022 03:23:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 1 Apr 2022 03:23:14 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 31 Mar 2022 20:23:11 -0700 From: Spike Du To: , , , CC: , Subject: [RFC 5/6] net/mlx5: add private API to config host port shaper Date: Fri, 1 Apr 2022 06:22:31 +0300 Message-ID: <20220401032232.1267376-6-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220401032232.1267376-1-spiked@nvidia.com> References: <20220401032232.1267376-1-spiked@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8344230f-fc40-47e9-3d91-08da138ef54a X-MS-TrafficTypeDiagnostic: BN8PR12MB3218:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:23:14.6195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8344230f-fc40-47e9-3d91-08da138ef54a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3218 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Host port shaper can be configured with QSHR(QoS Shaper Host Register). Add check in build files to enable this function or not. The host shaper configuration affects all the ethdev ports belonging to the same host port. Host shaper can configure shaper rate and lwm-triggered for a host port. The shaper limits the rate of traffic from host port to wire port. If lwm-triggered is enabled, a 100Mbps shaper is enabled automatically when one of the host port's Rx queues receives LWM(Limit Watermark) event. Signed-off-by: Spike Du --- doc/guides/nics/mlx5.rst | 7 +++ doc/guides/rel_notes/release_22_03.rst | 1 + drivers/common/mlx5/linux/meson.build | 21 +++++-- drivers/common/mlx5/mlx5_prm.h | 25 ++++++++ drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_rx.c | 104 +++++++++++++++++++++++++++++++++ drivers/net/mlx5/rte_pmd_mlx5.h | 30 ++++++++++ drivers/net/mlx5/version.map | 1 + 8 files changed, 187 insertions(+), 4 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 0e983a6..35210c1 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -93,6 +93,7 @@ Features - Sub-Function representors. - Sub-Function. - Rx queue LWM (Limit WaterMark) configuration. +- Host shaper support. Limitations @@ -511,6 +512,12 @@ Limitations - LWM: - Doesn't support shared Rx queue and Hairpin Rx queue. +- Host shaper: + + - Support BlueField series NIC from BlueField 2. + - When configure host shaper with MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED flag set, + only rate 0 and 100Mbps are supported. + Statistics ---------- diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 0c9d3b6..3ab4388 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -192,6 +192,7 @@ New Features Updated the Mellanox mlx5 driver with new features and improvements, including: * Added Rx queue LWM(Limit WaterMark) support. + * Added host shaper support. * **Updated Marvell cnxk crypto PMD.** diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index ed48245..c88c184 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -16,8 +16,9 @@ if dlopen_ibverbs ] endif -libnames = [ 'mlx5', 'ibverbs' ] +libnames = [ 'mlx5', 'ibverbs', 'mtcr_ul' ] libs = [] +libmtcr_ul_found = false foreach libname:libnames lib = dependency('lib' + libname, static:static_ibverbs, required:false, method: 'pkg-config') if not lib.found() and not static_ibverbs @@ -28,10 +29,16 @@ foreach libname:libnames if not static_ibverbs and not dlopen_ibverbs ext_deps += lib endif + if libname == 'mtcr_ul' + libmtcr_ul_found = true + ext_deps += lib + endif else - build = false - reason = 'missing dependency, "' + libname + '"' - subdir_done() + if libname != 'mtcr_ul' + build = false + reason = 'missing dependency, "' + libname + '"' + subdir_done() + endif endif endforeach if static_ibverbs or dlopen_ibverbs @@ -205,6 +212,12 @@ has_sym_args = [ [ 'HAVE_MLX5_IBV_IMPORT_CTX_PD_AND_MR', 'infiniband/verbs.h', 'ibv_import_device' ], ] +if libmtcr_ul_found + has_sym_args += [ + [ 'HAVE_MLX5_MSTFLINT', 'mstflint/mtcr.h', + 'mopen'], + ] +endif config = configuration_data() foreach arg:has_sym_args config.set(arg[0], cc.has_header_symbol(arg[1], arg[2], dependencies: libs)) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 23b13e3..3559927 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3768,6 +3768,7 @@ enum { MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, + MLX5_QSHR_REGISTER_ID = 0x4030, }; struct mlx5_ifc_register_mtutc_bits { @@ -3782,6 +3783,30 @@ struct mlx5_ifc_register_mtutc_bits { u8 time_adjustment[0x20]; }; +struct mlx5_ifc_ets_global_config_register_bits { + u8 reserved_at_0[0x2]; + u8 rate_limit_update[0x1]; + u8 reserved_at_3[0x29]; + u8 max_bw_units[0x4]; + u8 reserved_at_48[0x8]; + u8 max_bw_value[0x8]; +}; + +#define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0 +#define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3 +#define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4 + +struct mlx5_ifc_register_qshr_bits { + u8 reserved_at_0[0x4]; + u8 connected_host[0x1]; + u8 vqos[0x1]; + u8 fast_response[0x1]; + u8 reserved_at_7[0x1]; + u8 local_port[0x8]; + u8 reserved_at_16[0x230]; + struct mlx5_ifc_ets_global_config_register_bits global_config; +}; + #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 515ff33..5dfd375 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1267,6 +1267,8 @@ struct mlx5_dev_ctx_shared { void *devx_channel_lwm; struct rte_intr_handle *intr_handle_lwm; pthread_mutex_t lwm_config_lock; + uint32_t host_shaper_rate:8; + uint32_t lwm_triggered:1; /* Availability of mreg_c's. */ struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 0390412..6d5d11b 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -28,6 +28,9 @@ #include "mlx5_rxtx.h" #include "mlx5_devx.h" #include "mlx5_rx.h" +#ifdef HAVE_MLX5_MSTFLINT +#include +#endif static __rte_always_inline uint32_t rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe, @@ -1302,3 +1305,104 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) pthread_mutex_unlock(&priv->sh->lwm_config_lock); return ret; } + +/** + * Mlx5 access register function to configure host shaper. + * It calls API in libmtcr_ul to access QSHR(Qos Shaper Host Register) + * in firmware. + * + * @param dev + * Pointer to rte_eth_dev. + * @param lwm_triggered + * Flag to enable/disable lwm_triggered bit in QSHR. + * @param rate + * Host shaper rate, unit is 100Mbps, set to 0 means disable the shaper. + * @return + * 0 : operation success. + * Otherwise: + * - ENOENT - no ibdev interface. + * - EBUSY - the register access unit is busy. + * - EIO - the register access command meets IO error. + */ +static int +mlxreg_config_host_shaper(struct rte_eth_dev *dev, + bool lwm_triggered, uint8_t rate) +{ +#ifdef HAVE_MLX5_MSTFLINT + struct mlx5_priv *priv = dev->data->dev_private; + uint32_t data[MLX5_ST_SZ_DW(register_qshr)] = {0}; + int rc, retry_count = 3; + mfile *mf = NULL; + int status; + void *ptr; + + mf = mopen(priv->sh->ibdev_name); + if (!mf) { + DRV_LOG(WARNING, "mopen failed\n"); + rte_errno = ENOENT; + return -rte_errno; + } + MLX5_SET(register_qshr, data, connected_host, 1); + MLX5_SET(register_qshr, data, fast_response, lwm_triggered ? 1 : 0); + MLX5_SET(register_qshr, data, local_port, 1); + ptr = MLX5_ADDR_OF(register_qshr, data, global_config); + MLX5_SET(ets_global_config_register, ptr, rate_limit_update, 1); + MLX5_SET(ets_global_config_register, ptr, max_bw_units, + rate ? ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS : + ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED); + MLX5_SET(ets_global_config_register, ptr, max_bw_value, rate); + do { + rc = maccess_reg(mf, + MLX5_QSHR_REGISTER_ID, + MACCESS_REG_METHOD_SET, + (u_int32_t *)&data[0], + sizeof(data), + sizeof(data), + sizeof(data), + &status); + if ((rc != ME_ICMD_STATUS_IFC_BUSY && + status != ME_REG_ACCESS_BAD_PARAM) || + !(mf->flags & MDEVS_REM)) { + break; + } + DRV_LOG(WARNING, "%s retry.", __func__); + usleep(10000); + } while (retry_count-- > 0); + mclose(mf); + rte_errno = (rc == ME_REG_ACCESS_DEV_BUSY) ? EBUSY : EIO; + return rc ? -rte_errno : 0; +#else + (void)dev; + (void)lwm_triggered; + (void)rate; + return -1; +#endif +} + +int rte_pmd_mlx5_config_host_shaper(int port_id, uint8_t rate, + uint32_t flags) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct mlx5_priv *priv = dev->data->dev_private; + bool lwm_triggered = + !!(flags & RTE_BIT32(MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED)); + + if (!lwm_triggered) { + priv->sh->host_shaper_rate = rate; + } else { + switch (rate) { + case 0: + /* Rate 0 means disable lwm_triggered. */ + priv->sh->lwm_triggered = 0; + break; + case 1: + /* Rate 1 means enable lwm_triggered. */ + priv->sh->lwm_triggered = 1; + break; + default: + return -ENOTSUP; + } + } + return mlxreg_config_host_shaper(dev, priv->sh->lwm_triggered, + priv->sh->host_shaper_rate); +} diff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h index 4d2fb42..3a32463 100644 --- a/drivers/net/mlx5/rte_pmd_mlx5.h +++ b/drivers/net/mlx5/rte_pmd_mlx5.h @@ -141,6 +141,36 @@ int rte_pmd_mlx5_config_rxq_lwm(uint16_t port_id, uint16_t rxq_id, uint8_t lwm, lwm_event_rxq_limit_reached_t cb); +/** + * The rate of the host port shaper will be updated directly at the next + * LWM event to the rate that comes with this flag set; set rate 0 + * to disable this rate update. + * Unset this flag to update the rate of the host port shaper directly in + * the API call; use rate 0 to disable the current shaper. + */ +#define MLX5_HOST_SHAPER_FLAG_LWM_TRIGGERED 0 + +/** + * Configure an HW shaper to limit Rx rate for a host port. + * The configuration will affect all the ethdev ports belonging to + * the same rte_device. + * + * @param[in] port_id + * The port identifier of the Ethernet device. + * @param[in] rate + * Unit is 100Mbps, setting the rate to 0 disables the shaper. + * @param[in] flags + * Host shaper flags. + * @return + * 0 : operation success. + * Otherwise: + * - ENOENT - no ibdev interface. + * - EBUSY - the register access unit is busy. + * - EIO - the register access command meets IO error. + */ +__rte_experimental +int rte_pmd_mlx5_config_host_shaper(int port_id, uint8_t rate, uint32_t flags); + #ifdef __cplusplus } #endif diff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map index 8c965dd..5029e19 100644 --- a/drivers/net/mlx5/version.map +++ b/drivers/net/mlx5/version.map @@ -13,4 +13,5 @@ EXPERIMENTAL { rte_pmd_mlx5_external_rx_queue_id_map; rte_pmd_mlx5_external_rx_queue_id_unmap; rte_pmd_mlx5_config_rxq_lwm; + rte_pmd_mlx5_config_host_shaper; };