From patchwork Wed Apr 13 16:09:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 109651 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13801A0508; Wed, 13 Apr 2022 10:12:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 27BAA42838; Wed, 13 Apr 2022 10:11:35 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 5164542811 for ; Wed, 13 Apr 2022 10:11:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649837493; x=1681373493; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rPki7LM4lZ8ZSBqMaBam3rsY2yYXGCMWtpr8cL4jZuU=; b=ICPs4WnomQnZMFxO6zpmAHgIhLGcdZ/gvlWlVI7CN8T14mLgniDBXdu1 Q5RywOiYgftxNQmohGVE9dJUFqKp6xz+GqIlvFmuhEQo5WPAsFaGVXXV4 Q5aq5RPQNfM4YVYLg2ELZTjYwpf9O4GxTK6ZOkVqqfXAT+vv0hJbzmN1M 0jwrYlmWlM6nURGTc/8qIImfrfE5n4GwbXDBKt848s2eeetIY3xyOp3bu 2UMXLU2gzpCW2FCNn8M3sZoBW63B/8fFsYLPRz31VukszVJ4I65wapyq/ H1SH8p8LLK1UNPKJw8Ehxhl9YkcjApW2PQFaHkApYhQAv9uqAtYpeDK7v Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10315"; a="287630056" X-IronPort-AV: E=Sophos;i="5.90,256,1643702400"; d="scan'208";a="287630056" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2022 01:11:32 -0700 X-IronPort-AV: E=Sophos;i="5.90,256,1643702400"; d="scan'208";a="526847734" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2022 01:11:30 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Alvin Zhang , Junfeng Guo , Kevin Liu Subject: [PATCH v2 19/33] net/ice: support new patterns of TCP and UDP Date: Wed, 13 Apr 2022 16:09:18 +0000 Message-Id: <20220413160932.2074781-20-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220413160932.2074781-1-kevinx.liu@intel.com> References: <20220407105706.18889-1-kevinx.liu@intel.com> <20220413160932.2074781-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alvin Zhang Add definitions and pattern entries for below TCP and UDP patterns: MAC/VLAN/IPv4/TCP MAC/VLAN/IPv4/UDP Signed-off-by: Junfeng Guo Signed-off-by: Alvin Zhang Signed-off-by: Kevin Liu --- drivers/net/ice/ice_switch_filter.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index a8cb70ee0c..44046f803c 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -62,6 +62,10 @@ ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \ ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT) +#define ICE_SW_INSET_MAC_VLAN_IPV4_TCP ( \ + ICE_SW_INSET_MAC_VLAN | ICE_SW_INSET_MAC_IPV4_TCP) +#define ICE_SW_INSET_MAC_VLAN_IPV4_UDP ( \ + ICE_SW_INSET_MAC_VLAN | ICE_SW_INSET_MAC_IPV4_UDP) #define ICE_SW_INSET_MAC_IPV6 ( \ ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ ICE_INSET_IPV6_TC | ICE_INSET_IPV6_HOP_LIMIT | \ @@ -234,6 +238,8 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = { {pattern_eth_ipv4_udp, ICE_SW_INSET_MAC_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv4_tcp, ICE_SW_INSET_MAC_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_vlan_ipv4, ICE_SW_INSET_MAC_VLAN_IPV4, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_vlan_ipv4_tcp, ICE_SW_INSET_MAC_VLAN_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE}, + {pattern_eth_vlan_ipv4_udp, ICE_SW_INSET_MAC_VLAN_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6, ICE_SW_INSET_MAC_IPV6, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_udp, ICE_SW_INSET_MAC_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_ipv6_tcp, ICE_SW_INSET_MAC_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},