diff mbox series

[2/2] net/mlx5: fix LRO configuration in drop RxQ

Message ID 20220425093020.125319-3-michaelba@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: LRO fixes |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

Michael Baum April 25, 2022, 9:30 a.m. UTC 
  The driver wrongly set the LRO configurations to the TIR of the DevX
drop queue even when LRO is not supported.
Actually, the LRO configuration is not relevant to the drop queue at
all.

This causes failure in the initialization of the device, which doesn't
support LRO where the drop queue is created.

Probably, the drop queue creation by DevX missed the fact that LRO is
set by default in the TIR creation function and didn't unset it in the
drop queue case like other cases that unset LRO.

Move the default LRO configuration to unset it and set it only in the
case of all the TIR queues configured with LRO.

Fixes: bc5bee028ebc ("net/mlx5: create drop queue using DevX")
Cc: dkozlyuk@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/mlx5_devx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index 5ab092a259..03c0fac32f 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -715,7 +715,7 @@  mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
 	bool is_hairpin;
-	bool lro = true;
+	bool lro = false;
 	uint32_t i;
 
 	/* NULL queues designate drop queue. */
@@ -724,9 +724,9 @@  mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
 	} else if (mlx5_is_external_rxq(dev, ind_tbl->queues[0])) {
 		/* External RxQ supports neither Hairpin nor LRO. */
 		is_hairpin = false;
-		lro = false;
 	} else {
 		is_hairpin = mlx5_rxq_is_hairpin(dev, ind_tbl->queues[0]);
+		lro = true;
 		/* Enable TIR LRO only if all the queues were configured for. */
 		for (i = 0; i < ind_tbl->queues_n; ++i) {
 			struct mlx5_rxq_data *rxq_i =
@@ -776,6 +776,7 @@  mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
 	if (dev->data->dev_conf.lpbk_mode)
 		tir_attr->self_lb_block = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
 	if (lro) {
+		MLX5_ASSERT(priv->sh->dev_cap.lro_supported);
 		tir_attr->lro_timeout_period_usecs = priv->config.lro_timeout;
 		tir_attr->lro_max_msg_sz = priv->max_lro_msg_size;
 		tir_attr->lro_enable_mask =