From patchwork Thu Apr 28 02:59:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 110396 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9043A0503; Thu, 28 Apr 2022 05:22:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9BD364281B; Thu, 28 Apr 2022 05:21:34 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 3A56142805 for ; Thu, 28 Apr 2022 05:21:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651116090; x=1682652090; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hI498RhFk32E++GG9QEjfIi1EDurQQi+TtHssRWjSVk=; b=liKmZr0SEYmMwLGftg8cwHwLOrIgOcUZaTqhLiomQfcx+bin6cNZHPaH I9cfxyF2lieD8YX3RNUBQ5SdRxGGq0gepdEm7atx+WFnHB/YmNv9l51w0 E/B5rPPCOCV8Oa+40whsTV91hhR3/il76RzUDEi2/JV5v+bfcEaVVNCm6 4OeS3sRTZvmZm/MTIQihn8q6gNeZCBAv61r4t/jB61xdjfZm8vmdU0hpI Qrfl7OTW3YOdR/SiVy4gb7tvJ6+wld/ob3lOzWV5r2Yei7z/9P+5IEyDo zZxZqbfmLefzmFrHhprbNmYZgPjALc5G7ICpw6ouAR5KMD6jgDV3zN6Pk g==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="253526054" X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="253526054" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 20:21:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,295,1643702400"; d="scan'208";a="661534586" Received: from npg-wuwenjun-dpdk-01.sh.intel.com ([10.67.110.181]) by fmsmga002.fm.intel.com with ESMTP; 27 Apr 2022 20:21:28 -0700 From: Wenjun Wu To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com Subject: [PATCH v8 8/9] net/ice: support queue group priority configuration Date: Thu, 28 Apr 2022 10:59:13 +0800 Message-Id: <20220428025914.3475281-9-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428025914.3475281-1-wenjun1.wu@intel.com> References: <20220329014813.1092054-1-wenjun1.wu@intel.com> <20220428025914.3475281-1-wenjun1.wu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds queue group priority configuration support. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_tm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ice/ice_tm.c b/drivers/net/ice/ice_tm.c index 4d7bb9102c..f604523ead 100644 --- a/drivers/net/ice/ice_tm.c +++ b/drivers/net/ice/ice_tm.c @@ -764,6 +764,15 @@ static int ice_hierarchy_commit(struct rte_eth_dev *dev, goto fail_clear; } } + priority = 7 - tm_node->priority; + ret_val = ice_sched_cfg_sibl_node_prio_lock(hw->port_info, qgroup_sched_node, + priority); + if (ret_val) { + error->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY; + PMD_DRV_LOG(ERR, "configure queue group %u priority failed", + tm_node->priority); + goto fail_clear; + } idx_qg++; if (idx_qg >= nb_qg) { idx_qg = 0;