From patchwork Fri Apr 29 09:19:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 110460 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 164F5A0093; Fri, 29 Apr 2022 03:22:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 07AEE4281C; Fri, 29 Apr 2022 03:22:29 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id C2E36410E3 for ; Fri, 29 Apr 2022 03:22:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651195342; x=1682731342; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RAa+apHcTp9O+RYMbi4sG4AScyabm2VxBAfd6Ubq3vg=; b=dZaipDmmUytGJkY2h0f+KdX/AgelOFWgOzkMa5b5eZZh8kzVRyUq6Zum 7mlVwJXwtTA/CP3qZEDy8GlLcSTAKdkoIh2Fkh11Uk/MFF7tBz5U1+V/S 7HggD5khjKqOqmYTf/QEMcnFBLaYg7hKRHTTzsGA8N5HQuw4+cpuz3rlP ldDPPS9NeWonIL49xhO7Dar7qOwY4NfbKGzf4dE+Np0qOYTuUTyZ+bbxn CsgVXkQOMN4okT8yzJxlyepkfGBzmHHx4FGh/R4vzVXSEtswPz7e8bWSc +lSf0m9hBZ7Uh1FMIBv97dOTrs8W51wPD6Or0yzlXeFLqC98v9JbfCKpP A==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="266013642" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="266013642" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 18:22:21 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="581767752" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 18:22:19 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH v7 01/12] net/ice: support for RSS RETA configure in DCF mode Date: Fri, 29 Apr 2022 09:19:47 +0000 Message-Id: <20220429091958.3103384-2-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220429091958.3103384-1-kevinx.liu@intel.com> References: <20220427181301.1414196-1-kevinx.liu@intel.com> <20220429091958.3103384-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang RSS RETA should be updated and queried by application, Add related ops ('.reta_update', '.reta_query') for DCF. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- doc/guides/nics/features/ice_dcf.ini | 1 + doc/guides/rel_notes/release_22_07.rst | 3 + drivers/net/ice/ice_dcf.c | 2 +- drivers/net/ice/ice_dcf.h | 1 + drivers/net/ice/ice_dcf_ethdev.c | 77 ++++++++++++++++++++++++++ 5 files changed, 83 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/ice_dcf.ini b/doc/guides/nics/features/ice_dcf.ini index 54073f0b88..5221c99a9c 100644 --- a/doc/guides/nics/features/ice_dcf.ini +++ b/doc/guides/nics/features/ice_dcf.ini @@ -15,6 +15,7 @@ L3 checksum offload = P L4 checksum offload = P Inner L3 checksum = P Inner L4 checksum = P +RSS reta update = Y Basic stats = Y Linux = Y x86-32 = Y diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 90123bb807..1f07d3e1b3 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -60,6 +60,9 @@ New Features * Added Tx QoS queue rate limitation support. * Added quanta size configuration support. +* **Updated Intel ice driver.** + + * Added support for RSS RETA configure in DCF mode. Removed Items ------------- diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 7f0c074b01..070d1b71ac 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -790,7 +790,7 @@ ice_dcf_configure_rss_key(struct ice_dcf_hw *hw) return err; } -static int +int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw) { struct virtchnl_rss_lut *rss_lut; diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index 6ec766ebda..b2c6aa2684 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -122,6 +122,7 @@ int ice_dcf_send_aq_cmd(void *dcf_hw, struct ice_aq_desc *desc, int ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw); int ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); +int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); int ice_dcf_configure_queues(struct ice_dcf_hw *hw); int ice_dcf_config_irq_map(struct ice_dcf_hw *hw); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 59610e058f..1ac66ed990 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -761,6 +761,81 @@ ice_dcf_dev_flow_ops_get(struct rte_eth_dev *dev, return 0; } +static int +ice_dcf_dev_rss_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + uint8_t *lut; + uint16_t i, idx, shift; + int ret; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + if (reta_size != hw->vf_res->rss_lut_size) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number of hardware can " + "support (%d)", reta_size, hw->vf_res->rss_lut_size); + return -EINVAL; + } + + lut = rte_zmalloc("rss_lut", reta_size, 0); + if (!lut) { + PMD_DRV_LOG(ERR, "No memory can be allocated"); + return -ENOMEM; + } + /* store the old lut table temporarily */ + rte_memcpy(lut, hw->rss_lut, reta_size); + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + lut[i] = reta_conf[idx].reta[shift]; + } + + rte_memcpy(hw->rss_lut, lut, reta_size); + /* send virtchnnl ops to configure rss*/ + ret = ice_dcf_configure_rss_lut(hw); + if (ret) /* revert back */ + rte_memcpy(hw->rss_lut, lut, reta_size); + rte_free(lut); + + return ret; +} + +static int +ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + uint16_t i, idx, shift; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + if (reta_size != hw->vf_res->rss_lut_size) { + PMD_DRV_LOG(ERR, "The size of hash lookup table configured " + "(%d) doesn't match the number of hardware can " + "support (%d)", reta_size, hw->vf_res->rss_lut_size); + return -EINVAL; + } + + for (i = 0; i < reta_size; i++) { + idx = i / RTE_ETH_RETA_GROUP_SIZE; + shift = i % RTE_ETH_RETA_GROUP_SIZE; + if (reta_conf[idx].mask & (1ULL << shift)) + reta_conf[idx].reta[shift] = hw->rss_lut[i]; + } + + return 0; +} + #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4) #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6) #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t) @@ -1107,6 +1182,8 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .udp_tunnel_port_add = ice_dcf_dev_udp_tunnel_port_add, .udp_tunnel_port_del = ice_dcf_dev_udp_tunnel_port_del, .tm_ops_get = ice_dcf_tm_ops_get, + .reta_update = ice_dcf_dev_rss_reta_update, + .reta_query = ice_dcf_dev_rss_reta_query, }; static int