diff mbox series

[v2,1/2] config/arm: add SVE ACLE control flag

Message ID 20220507093943.2065586-1-rbhansali@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series [v2,1/2] config/arm: add SVE ACLE control flag |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Rahul Bhansali May 7, 2022, 9:39 a.m. UTC 
  This add the control flag for SVE ACLE to enable or disable
RTE_HAS_SVE_ACLE macro in the build.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2:
- Renamed the flag to sve_acle from sve
- Added double-indent.

 config/arm/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

--
2.25.1

Comments

fengchengwen May 9, 2022, 12:49 a.m. UTC | #1 
On 2022/5/7 17:39, Rahul Bhansali wrote:
> This add the control flag for SVE ACLE to enable or disable
> RTE_HAS_SVE_ACLE macro in the build.
> 
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
> Changes in v2:
> - Renamed the flag to sve_acle from sve
> - Added double-indent.
> 
>  config/arm/meson.build | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 8aead74086..2e12b541ef 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
>      compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
>  endif
> 
> -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> +        soc_config.get('sve_acle', true))
>      compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
>      if (cc.check_header('arm_sve.h'))

the above sve_acle also impact RTE_CPUFLAG_SVE which don't mentioned in commit log.
suggest add soc_config.get('sve_acle', true) in above if statement.

>          dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> --
> 2.25.1
> 
> 
> .
>
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8aead74086..2e12b541ef 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -603,7 +603,8 @@  if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
     compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 endif

-if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
+if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
+        soc_config.get('sve_acle', true))
     compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
     if (cc.check_header('arm_sve.h'))
         dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)