@@ -88,9 +88,6 @@
/* rte_power defines */
#define RTE_MAX_LCORE_FREQS 64
-/* rte_sched defines */
-#undef RTE_SCHED_CMAN
-
/* rte_graph defines */
#define RTE_GRAPH_BURST_SIZE 256
#define RTE_LIBRTE_GRAPH_STATS 1
@@ -420,11 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_CMAN
#define WRED_SUPPORTED 1
-#else
-#define WRED_SUPPORTED 0
-#endif
#define STATS_MASK_DEFAULT \
(RTE_TM_STATS_N_PKTS | \
@@ -2300,8 +2296,6 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t tc_id)
return NULL;
}
-#ifdef RTE_SCHED_CMAN
-
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
{
@@ -2325,12 +2319,6 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
}
}
-#else
-
-#define wred_profiles_set(dev, subport_id)
-
-#endif
-
static struct tm_shared_shaper *
tm_tc_shared_shaper_get(struct rte_eth_dev *dev, struct tm_node *tc_node)
{
@@ -17,7 +17,6 @@ static uint32_t n_subport_profiles;
static struct rte_sched_pipe_params
pipe_profile[TMGR_PIPE_PROFILE_MAX];
-#ifdef RTE_SCHED_CMAN
static struct rte_sched_cman_params cman_params = {
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
@@ -86,7 +85,6 @@ static struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
static uint32_t n_pipe_profiles;
@@ -96,9 +94,7 @@ static const struct rte_sched_subport_params subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
};
static struct tmgr_port_list tmgr_port_list;
@@ -229,13 +229,15 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
subport_p->cman_params->cman_mode = cman_p.cman_mode;
+ if (subport_p->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)
+ return;
+
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
if (subport_p->cman_params->cman_mode ==
RTE_SCHED_CMAN_RED) {
@@ -261,7 +263,6 @@ void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
}
}
}
-#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
@@ -276,12 +277,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
- .cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
+ if (cman_params.cman_mode != RTE_SCHED_CMAN_NONE) {
+ cman_params.cman_mode = RTE_SCHED_CMAN_NONE;
+ }
+
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
@@ -387,7 +390,6 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
-#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -465,9 +467,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_CMAN
set_subport_cman_params(subport_params+i, cman_params);
-#endif
}
}
@@ -12,10 +12,8 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
-#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
-#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
@@ -201,7 +201,6 @@ static struct rte_sched_subport_profile_params
},
};
-#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
@@ -271,7 +270,6 @@ struct rte_sched_cman_params cman_params = {
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
-#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
@@ -281,9 +279,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
-#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
-#endif /* RTE_SCHED_CMAN */
},
};
@@ -153,9 +153,7 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
-#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
-#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);
@@ -142,68 +142,68 @@ tc 12 wrr weights = 1 1 1 1
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
-[pie]
-tc 0 qdelay ref = 15
-tc 0 max burst = 150
-tc 0 update interval = 15
-tc 0 tailq th = 64
-
-tc 1 qdelay ref = 15
-tc 1 max burst = 150
-tc 1 update interval = 15
-tc 1 tailq th = 64
-
-tc 2 qdelay ref = 15
-tc 2 max burst = 150
-tc 2 update interval = 15
-tc 2 tailq th = 64
-
-tc 3 qdelay ref = 15
-tc 3 max burst = 150
-tc 3 update interval = 15
-tc 3 tailq th = 64
-
-tc 4 qdelay ref = 15
-tc 4 max burst = 150
-tc 4 update interval = 15
-tc 4 tailq th = 64
-
-tc 5 qdelay ref = 15
-tc 5 max burst = 150
-tc 5 update interval = 15
-tc 5 tailq th = 64
-
-tc 6 qdelay ref = 15
-tc 6 max burst = 150
-tc 6 update interval = 15
-tc 6 tailq th = 64
-
-tc 7 qdelay ref = 15
-tc 7 max burst = 150
-tc 7 update interval = 15
-tc 7 tailq th = 64
-
-tc 8 qdelay ref = 15
-tc 8 max burst = 150
-tc 8 update interval = 15
-tc 8 tailq th = 64
-
-tc 9 qdelay ref = 15
-tc 9 max burst = 150
-tc 9 update interval = 15
-tc 9 tailq th = 64
-
-tc 10 qdelay ref = 15
-tc 10 max burst = 150
-tc 10 update interval = 15
-tc 10 tailq th = 64
-
-tc 11 qdelay ref = 15
-tc 11 max burst = 150
-tc 11 update interval = 15
-tc 11 tailq th = 64
-
-tc 12 qdelay ref = 15
-tc 12 max burst = 150
-tc 12 update interval = 15
-tc 12 tailq th = 64
+;[pie]
+;tc 0 qdelay ref = 15
+;tc 0 max burst = 150
+;tc 0 update interval = 15
+;tc 0 tailq th = 64
+
+;tc 1 qdelay ref = 15
+;tc 1 max burst = 150
+;tc 1 update interval = 15
+;tc 1 tailq th = 64
+
+;tc 2 qdelay ref = 15
+;tc 2 max burst = 150
+;tc 2 update interval = 15
+;tc 2 tailq th = 64
+
+;tc 3 qdelay ref = 15
+;tc 3 max burst = 150
+;tc 3 update interval = 15
+;tc 3 tailq th = 64
+
+;tc 4 qdelay ref = 15
+;tc 4 max burst = 150
+;tc 4 update interval = 15
+;tc 4 tailq th = 64
+
+;tc 5 qdelay ref = 15
+;tc 5 max burst = 150
+;tc 5 update interval = 15
+;tc 5 tailq th = 64
+
+;tc 6 qdelay ref = 15
+;tc 6 max burst = 150
+;tc 6 update interval = 15
+;tc 6 tailq th = 64
+
+;tc 7 qdelay ref = 15
+;tc 7 max burst = 150
+;tc 7 update interval = 15
+;tc 7 tailq th = 64
+
+;tc 8 qdelay ref = 15
+;tc 8 max burst = 150
+;tc 8 update interval = 15
+;tc 8 tailq th = 64
+
+;tc 9 qdelay ref = 15
+;tc 9 max burst = 150
+;tc 9 update interval = 15
+;tc 9 tailq th = 64
+
+;tc 10 qdelay ref = 15
+;tc 10 max burst = 150
+;tc 10 update interval = 15
+;tc 10 tailq th = 64
+
+;tc 11 qdelay ref = 15
+;tc 11 max burst = 150
+;tc 11 update interval = 15
+;tc 11 tailq th = 64
+
+;tc 12 qdelay ref = 15
+;tc 12 max burst = 150
+;tc 12 update interval = 15
+;tc 12 tailq th = 64
new file mode 100644
@@ -0,0 +1,142 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+[pie]
+tc 0 qdelay ref = 15
+tc 0 max burst = 150
+tc 0 update interval = 15
+tc 0 tailq th = 64
+
+tc 1 qdelay ref = 15
+tc 1 max burst = 150
+tc 1 update interval = 15
+tc 1 tailq th = 64
+
+tc 2 qdelay ref = 15
+tc 2 max burst = 150
+tc 2 update interval = 15
+tc 2 tailq th = 64
+
+tc 3 qdelay ref = 15
+tc 3 max burst = 150
+tc 3 update interval = 15
+tc 3 tailq th = 64
+
+tc 4 qdelay ref = 15
+tc 4 max burst = 150
+tc 4 update interval = 15
+tc 4 tailq th = 64
+
+tc 5 qdelay ref = 15
+tc 5 max burst = 150
+tc 5 update interval = 15
+tc 5 tailq th = 64
+
+tc 6 qdelay ref = 15
+tc 6 max burst = 150
+tc 6 update interval = 15
+tc 6 tailq th = 64
+
+tc 7 qdelay ref = 15
+tc 7 max burst = 150
+tc 7 update interval = 15
+tc 7 tailq th = 64
+
+tc 8 qdelay ref = 15
+tc 8 max burst = 150
+tc 8 update interval = 15
+tc 8 tailq th = 64
+
+tc 9 qdelay ref = 15
+tc 9 max burst = 150
+tc 9 update interval = 15
+tc 9 tailq th = 64
+
+tc 10 qdelay ref = 15
+tc 10 max burst = 150
+tc 10 update interval = 15
+tc 10 tailq th = 64
+
+tc 11 qdelay ref = 15
+tc 11 max burst = 150
+tc 11 update interval = 15
+tc 11 tailq th = 64
+
+tc 12 qdelay ref = 15
+tc 12 max burst = 150
+tc 12 update interval = 15
+tc 12 tailq th = 64
new file mode 100644
@@ -0,0 +1,143 @@
+; SPDX-License-Identifier: BSD-3-Clause
+; Copyright(c) 2010-2019 Intel Corporation.
+
+; This file enables the following hierarchical scheduler configuration for each
+; 10GbE output port:
+; * Single subport (subport 0):
+; - Subport rate set to 100% of port rate
+; - Each of the 13 traffic classes has rate set to 100% of port rate
+; * 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:
+; - Pipe rate set to 1/4K of port rate
+; - Each of the 13 traffic classes has rate set to 100% of pipe rate
+; - Within lowest priority traffic class (best-effort), the byte-level
+; WRR weights for the 4 queues of best effort traffic class are set
+; to 1:1:1:1
+;
+; For more details, please refer to chapter "Quality of Service (QoS) Framework"
+; of Data Plane Development Kit (DPDK) Programmer's Guide.
+
+; Port configuration
+[port]
+frame overhead = 24
+number of subports per port = 1
+
+; Subport configuration
+[subport 0]
+number of pipes per subport = 4096
+queue sizes = 64 64 64 64 64 64 64 64 64 64 64 64 64
+
+subport 0-8 = 0 ; These subports are configured with subport profile 0
+
+[subport profile 0]
+tb rate = 1250000000 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 1250000000 ; Bytes per second
+tc 1 rate = 1250000000 ; Bytes per second
+tc 2 rate = 1250000000 ; Bytes per second
+tc 3 rate = 1250000000 ; Bytes per second
+tc 4 rate = 1250000000 ; Bytes per second
+tc 5 rate = 1250000000 ; Bytes per second
+tc 6 rate = 1250000000 ; Bytes per second
+tc 7 rate = 1250000000 ; Bytes per second
+tc 8 rate = 1250000000 ; Bytes per second
+tc 9 rate = 1250000000 ; Bytes per second
+tc 10 rate = 1250000000 ; Bytes per second
+tc 11 rate = 1250000000 ; Bytes per second
+tc 12 rate = 1250000000 ; Bytes per second
+
+tc period = 10 ; Milliseconds
+
+pipe 0-4095 = 0 ; These pipes are configured with pipe profile 0
+
+; Pipe configuration
+[pipe profile 0]
+tb rate = 305175 ; Bytes per second
+tb size = 1000000 ; Bytes
+
+tc 0 rate = 305175 ; Bytes per second
+tc 1 rate = 305175 ; Bytes per second
+tc 2 rate = 305175 ; Bytes per second
+tc 3 rate = 305175 ; Bytes per second
+tc 4 rate = 305175 ; Bytes per second
+tc 5 rate = 305175 ; Bytes per second
+tc 6 rate = 305175 ; Bytes per second
+tc 7 rate = 305175 ; Bytes per second
+tc 8 rate = 305175 ; Bytes per second
+tc 9 rate = 305175 ; Bytes per second
+tc 10 rate = 305175 ; Bytes per second
+tc 11 rate = 305175 ; Bytes per second
+tc 12 rate = 305175 ; Bytes per second
+
+tc period = 40 ; Milliseconds
+
+tc 12 oversubscription weight = 1
+
+tc 12 wrr weights = 1 1 1 1
+
+; RED params per traffic class and color (Green / Yellow / Red)
+[red]
+tc 0 wred min = 48 40 32
+tc 0 wred max = 64 64 64
+tc 0 wred inv prob = 10 10 10
+tc 0 wred weight = 9 9 9
+
+tc 1 wred min = 48 40 32
+tc 1 wred max = 64 64 64
+tc 1 wred inv prob = 10 10 10
+tc 1 wred weight = 9 9 9
+
+tc 2 wred min = 48 40 32
+tc 2 wred max = 64 64 64
+tc 2 wred inv prob = 10 10 10
+tc 2 wred weight = 9 9 9
+
+tc 3 wred min = 48 40 32
+tc 3 wred max = 64 64 64
+tc 3 wred inv prob = 10 10 10
+tc 3 wred weight = 9 9 9
+
+tc 4 wred min = 48 40 32
+tc 4 wred max = 64 64 64
+tc 4 wred inv prob = 10 10 10
+tc 4 wred weight = 9 9 9
+
+tc 5 wred min = 48 40 32
+tc 5 wred max = 64 64 64
+tc 5 wred inv prob = 10 10 10
+tc 5 wred weight = 9 9 9
+
+tc 6 wred min = 48 40 32
+tc 6 wred max = 64 64 64
+tc 6 wred inv prob = 10 10 10
+tc 6 wred weight = 9 9 9
+
+tc 7 wred min = 48 40 32
+tc 7 wred max = 64 64 64
+tc 7 wred inv prob = 10 10 10
+tc 7 wred weight = 9 9 9
+
+tc 8 wred min = 48 40 32
+tc 8 wred max = 64 64 64
+tc 8 wred inv prob = 10 10 10
+tc 8 wred weight = 9 9 9
+
+tc 9 wred min = 48 40 32
+tc 9 wred max = 64 64 64
+tc 9 wred inv prob = 10 10 10
+tc 9 wred weight = 9 9 9
+
+tc 10 wred min = 48 40 32
+tc 10 wred max = 64 64 64
+tc 10 wred inv prob = 10 10 10
+tc 10 wred weight = 9 9 9
+
+tc 11 wred min = 48 40 32
+tc 11 wred max = 64 64 64
+tc 11 wred inv prob = 10 10 10
+tc 11 wred weight = 9 9 9
+
+tc 12 wred min = 48 40 32
+tc 12 wred max = 64 64 64
+tc 12 wred inv prob = 10 10 10
+tc 12 wred weight = 9 9 9
@@ -81,13 +81,11 @@ struct rte_sched_queue {
struct rte_sched_queue_extra {
struct rte_sched_queue_stats stats;
-#ifdef RTE_SCHED_CMAN
RTE_STD_C11
union {
struct rte_red red;
struct rte_pie pie;
};
-#endif
};
enum grinder_state {
@@ -179,7 +177,6 @@ struct rte_sched_subport {
/* Pipe queues size */
uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
-#ifdef RTE_SCHED_CMAN
bool cman_enabled;
enum rte_sched_cman_mode cman;
@@ -188,7 +185,6 @@ struct rte_sched_subport {
struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_pie_config pie_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
};
-#endif
/* Scheduling loop detection */
uint32_t pipe_loop;
@@ -1081,7 +1077,6 @@ rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)
rte_free(port);
}
-#ifdef RTE_SCHED_CMAN
static int
rte_sched_red_config(struct rte_sched_port *port,
struct rte_sched_subport *s,
@@ -1161,9 +1156,11 @@ rte_sched_cman_config(struct rte_sched_port *port,
else if (params->cman_params->cman_mode == RTE_SCHED_CMAN_PIE)
return rte_sched_pie_config(port, s, params, n_subports);
+ else if (params->cman_params->cman_mode == RTE_SCHED_CMAN_NONE)
+ return 1;
+
return -EINVAL;
}
-#endif
int
rte_sched_subport_config(struct rte_sched_port *port,
@@ -1254,19 +1251,20 @@ rte_sched_subport_config(struct rte_sched_port *port,
s->n_pipe_profiles = params->n_pipe_profiles;
s->n_max_pipe_profiles = params->n_max_pipe_profiles;
-#ifdef RTE_SCHED_CMAN
+ s->cman_enabled = false;
+
if (params->cman_params != NULL) {
- s->cman_enabled = true;
status = rte_sched_cman_config(port, s, params, n_subports);
if (status) {
- RTE_LOG(NOTICE, SCHED,
- "%s: CMAN configuration fails\n", __func__);
- return status;
+ if (status != 1) {
+ RTE_LOG(NOTICE, SCHED,
+ "%s: CMAN configuration fails\n", __func__);
+ return status;
+ }
+ } else {
+ s->cman_enabled = true;
}
- } else {
- s->cman_enabled = false;
}
-#endif
/* Scheduling loop detection */
s->pipe_loop = RTE_SCHED_PIPE_INVALID;
@@ -1825,14 +1823,10 @@ rte_sched_port_update_queue_stats_on_drop(struct rte_sched_subport *subport,
qe->stats.n_pkts_dropped += 1;
qe->stats.n_bytes_dropped += pkt_len;
-#ifdef RTE_SCHED_CMAN
if (subport->cman_enabled)
qe->stats.n_pkts_cman_dropped += n_pkts_cman_dropped;
-#endif
}
-#ifdef RTE_SCHED_CMAN
-
static inline int
rte_sched_port_cman_drop(struct rte_sched_port *port,
struct rte_sched_subport *subport,
@@ -1902,29 +1896,6 @@ uint32_t qindex, uint32_t pkt_len, uint64_t time) {
}
}
-#else
-
-static inline int rte_sched_port_cman_drop(struct rte_sched_port *port __rte_unused,
- struct rte_sched_subport *subport __rte_unused,
- struct rte_mbuf *pkt __rte_unused,
- uint32_t qindex __rte_unused,
- uint16_t qlen __rte_unused)
-{
- return 0;
-}
-
-#define rte_sched_port_red_set_queue_empty_timestamp(port, subport, qindex)
-
-static inline void
-rte_sched_port_pie_dequeue(struct rte_sched_subport *subport __rte_unused,
- uint32_t qindex __rte_unused,
- uint32_t pkt_len __rte_unused,
- uint64_t time __rte_unused) {
- /* do-nothing when RTE_SCHED_CMAN not defined */
-}
-
-#endif /* RTE_SCHED_CMAN */
-
#ifdef RTE_SCHED_DEBUG
static inline void
@@ -126,6 +126,7 @@ extern "C" {
* information, refer RFC8033.
*/
enum rte_sched_cman_mode {
+ RTE_SCHED_CMAN_NONE, /**< no RED|PIE cfg available */
RTE_SCHED_CMAN_RED, /**< Random Early Detection (RED) */
RTE_SCHED_CMAN_PIE, /**< Proportional Integral Controller Enhanced (PIE) */
};