From patchwork Tue May 24 08:42:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harman Kalra X-Patchwork-Id: 111711 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B1DF8A04FF; Tue, 24 May 2022 10:43:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 81CAD41104; Tue, 24 May 2022 10:43:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0DA4D400D6 for ; Tue, 24 May 2022 10:42:58 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24NNBSVk022568 for ; Tue, 24 May 2022 01:42:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=r49QqWDG9tuMlxHgGDujMnx2/mZ90RYBguqJDtbvli4=; b=Bgfm091baEJCbEeCHfs9gno9kG9hwpocQoQrbESroLJfktbeC+JMN2/ExPyDV5yxkaHj wIVE504j0Kj6jariuemQT9vl8VTZ6C64roL8Bi5oVOsWJYmRW3PHp/DLg1x4SJu8zjaq DAfivXLsnxffnP/JGXnuKdmRKYBDtuU/3uKE+6aOoCqj+QeKp+Uo94nBOqE50s1dJf2d G0+FFw8k50BoFeGuzxp7kMi6zcAKT9C1Ijklwg+4o73skkc99k/Nlb14QURvDzAyuPuy S1U1lG2PsjXs81Vd/+PAZ4uEEugOg+Jz4vpSak24i7abwI9AfQT3iBTr02HRPXslj2Dp fw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3g8kqjhrtk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 24 May 2022 01:42:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 24 May 2022 01:42:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 24 May 2022 01:42:56 -0700 Received: from localhost.localdomain (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 496E83F709F; Tue, 24 May 2022 01:42:55 -0700 (PDT) From: Harman Kalra To: , Harman Kalra Subject: [PATCH v3 03/11] net/octeontx: setting link attributes Date: Tue, 24 May 2022 14:12:27 +0530 Message-ID: <20220524084235.17796-3-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220524084235.17796-1-hkalra@marvell.com> References: <20220517173941.189330-2-hkalra@marvell.com> <20220524084235.17796-1-hkalra@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xXIC8BQgPxnuCT7OEJlrlXyO34ZRCBKV X-Proofpoint-GUID: xXIC8BQgPxnuCT7OEJlrlXyO34ZRCBKV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-24_06,2022-05-23_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support to configure link attributes like speed, duplex, negotiation. Signed-off-by: Harman Kalra --- drivers/net/octeontx/base/octeontx_bgx.c | 19 ++++++ drivers/net/octeontx/base/octeontx_bgx.h | 12 ++++ drivers/net/octeontx/octeontx_ethdev.c | 80 ++++++++++++++++++++++-- 3 files changed, 105 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c index ac856ff86d..1c6fa05ebc 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.c +++ b/drivers/net/octeontx/base/octeontx_bgx.c @@ -376,3 +376,22 @@ int octeontx_bgx_port_flow_ctrl_cfg(int port, done: return 0; } + +int octeontx_bgx_port_change_mode(int port, + octeontx_mbox_bgx_port_change_mode_t *cfg) +{ + int len = sizeof(octeontx_mbox_bgx_port_change_mode_t), res; + octeontx_mbox_bgx_port_change_mode_t conf; + struct octeontx_mbox_hdr hdr; + + hdr.coproc = OCTEONTX_BGX_COPROC; + hdr.msg = MBOX_BGX_PORT_CHANGE_MODE; + hdr.vfid = port; + + memcpy(&conf, cfg, len); + res = octeontx_mbox_send(&hdr, &conf, len, NULL, 0); + if (res < 0) + return -EACCES; + + return res; +} diff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h index d126a0b7fc..e4cfa3e73a 100644 --- a/drivers/net/octeontx/base/octeontx_bgx.h +++ b/drivers/net/octeontx/base/octeontx_bgx.h @@ -37,6 +37,7 @@ #define MBOX_BGX_PORT_GET_FIFO_CFG 18 #define MBOX_BGX_PORT_FLOW_CTRL_CFG 19 #define MBOX_BGX_PORT_SET_LINK_STATE 20 +#define MBOX_BGX_PORT_CHANGE_MODE 21 /* BGX port configuration parameters: */ typedef struct octeontx_mbox_bgx_port_conf { @@ -143,6 +144,15 @@ typedef struct octeontx_mbox_bgx_port_fc_cfg { bgx_port_fc_t fc_cfg; } octeontx_mbox_bgx_port_fc_cfg_t; +/* BGX change mode */ +typedef struct octeontx_mbox_bgx_port_change_mode { + uint16_t padding; + uint8_t qlm_mode; + bool autoneg; + uint8_t duplex; + uint32_t speed; +} octeontx_mbox_bgx_port_change_mode_t; + int octeontx_bgx_port_open(int port, octeontx_mbox_bgx_port_conf_t *conf); int octeontx_bgx_port_close(int port); int octeontx_bgx_port_start(int port); @@ -163,6 +173,8 @@ int octeontx_bgx_port_get_fifo_cfg(int port, octeontx_mbox_bgx_port_fifo_cfg_t *cfg); int octeontx_bgx_port_flow_ctrl_cfg(int port, octeontx_mbox_bgx_port_fc_cfg_t *cfg); +int octeontx_bgx_port_change_mode(int port, + octeontx_mbox_bgx_port_change_mode_t *cfg); #endif /* __OCTEONTX_BGX_H__ */ diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index 6469fd0a96..9b13e22089 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -31,6 +31,9 @@ */ uint16_t evdev_refcnt; +#define OCTEONTX_QLM_MODE_SGMII 7 +#define OCTEONTX_QLM_MODE_XFI 12 + struct evdev_priv_data { OFFLOAD_FLAGS; /*Sequence should not be changed */ } __rte_cache_aligned; @@ -50,7 +53,8 @@ enum octeontx_link_speed { OCTEONTX_LINK_SPEED_40G_R, OCTEONTX_LINK_SPEED_RESERVE1, OCTEONTX_LINK_SPEED_QSGMII, - OCTEONTX_LINK_SPEED_RESERVE2 + OCTEONTX_LINK_SPEED_RESERVE2, + OCTEONTX_LINK_SPEED_UNKNOWN = 255 }; RTE_LOG_REGISTER_SUFFIX(otx_net_logtype_mbox, mbox, NOTICE); @@ -139,6 +143,7 @@ octeontx_port_open(struct octeontx_nic *nic) nic->mcast_mode = bgx_port_conf.mcast_mode; nic->speed = bgx_port_conf.mode; + nic->duplex = RTE_ETH_LINK_FULL_DUPLEX; memset(&fifo_cfg, 0x0, sizeof(fifo_cfg)); res = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg); @@ -171,6 +176,67 @@ octeontx_link_status_print(struct rte_eth_dev *eth_dev, (int)(eth_dev->data->port_id)); } +static inline uint32_t +octeontx_parse_link_speeds(uint32_t link_speeds) +{ + uint32_t link_speed = OCTEONTX_LINK_SPEED_UNKNOWN; + + if (link_speeds & RTE_ETH_LINK_SPEED_40G) + link_speed = OCTEONTX_LINK_SPEED_40G_R; + + if (link_speeds & RTE_ETH_LINK_SPEED_10G) { + link_speed = OCTEONTX_LINK_SPEED_XAUI; + link_speed |= OCTEONTX_LINK_SPEED_RXAUI; + link_speed |= OCTEONTX_LINK_SPEED_10G_R; + } + + if (link_speeds & RTE_ETH_LINK_SPEED_5G) + link_speed = OCTEONTX_LINK_SPEED_QSGMII; + + if (link_speeds & RTE_ETH_LINK_SPEED_1G) + link_speed = OCTEONTX_LINK_SPEED_SGMII; + + return link_speed; +} + +static inline uint8_t +octeontx_parse_eth_link_duplex(uint32_t link_speeds) +{ + if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || + (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) + return RTE_ETH_LINK_HALF_DUPLEX; + else + return RTE_ETH_LINK_FULL_DUPLEX; +} + +static int +octeontx_apply_link_speed(struct rte_eth_dev *dev) +{ + struct octeontx_nic *nic = octeontx_pmd_priv(dev); + struct rte_eth_conf *conf = &dev->data->dev_conf; + octeontx_mbox_bgx_port_change_mode_t cfg; + + if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) + return 0; + + cfg.speed = octeontx_parse_link_speeds(conf->link_speeds); + cfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0; + cfg.duplex = octeontx_parse_eth_link_duplex(conf->link_speeds); + cfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ? + OCTEONTX_QLM_MODE_SGMII : + (conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ? + OCTEONTX_QLM_MODE_XFI : 0); + + if (cfg.speed != OCTEONTX_LINK_SPEED_UNKNOWN && + (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) { + nic->speed = cfg.speed; + nic->duplex = cfg.duplex; + return octeontx_bgx_port_change_mode(nic->port_id, &cfg); + } else { + return 0; + } +} + static void octeontx_link_status_update(struct octeontx_nic *nic, struct rte_eth_link *link) @@ -440,11 +506,6 @@ octeontx_dev_configure(struct rte_eth_dev *dev) txmode->offloads |= RTE_ETH_TX_OFFLOAD_MT_LOCKFREE; } - if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { - octeontx_log_err("setting link speed/duplex not supported"); - return -EINVAL; - } - if (conf->dcb_capability_en) { octeontx_log_err("DCB enable not supported"); return -EINVAL; @@ -621,6 +682,13 @@ octeontx_dev_start(struct rte_eth_dev *dev) goto error; } + /* Apply new link configurations if changed */ + ret = octeontx_apply_link_speed(dev); + if (ret) { + octeontx_log_err("Failed to set link configuration: %d", ret); + goto error; + } + /* * Tx start */