diff mbox series

[10/10] common/cnxk: support switching CPRI/ETH back and forth

Message ID 20220604162651.3503338-11-tduszynski@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series Sync BPHY changes |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-mellanox-Performance success Performance Testing PASS
ci/github-robot: build success github build: passed
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-compile-testing fail Testing issues
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/iol-abi-testing success Testing PASS

Commit Message

Tomasz Duszynski June 4, 2022, 4:26 p.m. UTC 
  Add support for toggling modes between ETH and CPRI on
newer MACs (RPM).

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.h    | 17 ++++++++++++++++-
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 14 ++++++++++++--
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 27 +++++++++++++++++++++++++--
 3 files changed, 53 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 4ce1316513..2b9a23f5b1 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -86,8 +86,20 @@  enum roc_bphy_cgx_eth_link_mode {
 	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
 };
 
+/* Supported CPRI modes */
+enum roc_bphy_cgx_eth_mode_cpri {
+	ROC_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT,
+	ROC_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT,
+	ROC_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT,
+	ROC_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT,
+	ROC_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT,
+	ROC_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT,
+	ROC_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT,
+};
+
 enum roc_bphy_cgx_mode_group {
 	ROC_BPHY_CGX_MODE_GROUP_ETH,
+	ROC_BPHY_CGX_MODE_GROUP_CPRI = 2,
 };
 
 struct roc_bphy_cgx_link_mode {
@@ -97,7 +109,10 @@  struct roc_bphy_cgx_link_mode {
 	unsigned int portm_idx;
 	enum roc_bphy_cgx_mode_group mode_group_idx;
 	enum roc_bphy_cgx_eth_link_speed speed;
-	enum roc_bphy_cgx_eth_link_mode mode;
+	union {
+		enum roc_bphy_cgx_eth_link_mode mode;
+		enum roc_bphy_cgx_eth_mode_cpri mode_cpri;
+	};
 };
 
 struct roc_bphy_cgx_link_info {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index f839a70f04..26def43564 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -118,8 +118,18 @@  cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
 			(enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx;
 		rlink_mode.speed =
 			(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
-		rlink_mode.mode =
-			(enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+		switch (link_mode->mode_group_idx) {
+		case CNXK_BPHY_CGX_MODE_GROUP_ETH:
+			rlink_mode.mode =
+				(enum roc_bphy_cgx_eth_link_mode)
+				link_mode->mode;
+			break;
+		case CNXK_BPHY_CGX_MODE_GROUP_CPRI:
+			rlink_mode.mode_cpri =
+				(enum roc_bphy_cgx_eth_mode_cpri)
+				link_mode->mode_cpri;
+			break;
+		}
 		ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
 		break;
 	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 7f326e3643..f9949fa313 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -168,9 +168,28 @@  enum cnxk_bphy_cgx_eth_link_mode {
 	__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
 };
 
+enum cnxk_bphy_cgx_eth_mode_cpri {
+	/** 2.4G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT,
+	/** 3.1G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT,
+	/** 4.9G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT,
+	/** 6.1G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT,
+	/** 9.8G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT,
+	/** 10.1G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT,
+	/** 24.3G Lane Rate */
+	CNXK_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT,
+};
+
 enum cnxk_bphy_cgx_mode_group {
 	/** ETH group */
 	CNXK_BPHY_CGX_MODE_GROUP_ETH,
+	/** CPRI group */
+	CNXK_BPHY_CGX_MODE_GROUP_CPRI = 2,
 };
 
 struct cnxk_bphy_cgx_msg_link_mode {
@@ -186,8 +205,12 @@  struct cnxk_bphy_cgx_msg_link_mode {
 	enum cnxk_bphy_cgx_mode_group mode_group_idx;
 	/** Link speed */
 	enum cnxk_bphy_cgx_eth_link_speed speed;
-	/** Link mode */
-	enum cnxk_bphy_cgx_eth_link_mode mode;
+	union {
+		/** Link mode */
+		enum cnxk_bphy_cgx_eth_link_mode mode;
+		/** CPRI mode */
+		enum cnxk_bphy_cgx_eth_mode_cpri mode_cpri;
+	};
 };
 
 struct cnxk_bphy_cgx_msg_link_info {