| Message ID | 20220622092808.1952992-1-radu.nicolau@intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | akhil goyal |
| Headers | show |
| Series | examples/ipsec-secgw: fix Tx checksum offload flag | expand |
| Context | Check | Description |
|---|---|---|
| ci/iol-abi-testing | warning | Testing issues |
| ci/iol-mellanox-Performance | success | Performance Testing PASS |
| ci/iol-intel-Functional | success | Functional Testing PASS |
| ci/iol-intel-Performance | success | Performance Testing PASS |
| ci/github-robot: build | success | github build: passed |
| ci/iol-x86_64-compile-testing | success | Testing PASS |
| ci/iol-x86_64-unit-testing | success | Testing PASS |
| ci/iol-aarch64-compile-testing | success | Testing PASS |
| ci/iol-aarch64-unit-testing | success | Testing PASS |
| ci/intel-Testing | success | Testing PASS |
| ci/Intel-compilation | success | Compilation OK |
| ci/checkpatch | success | coding style OK |
> -----Original Message----- > From: Radu Nicolau <radu.nicolau@intel.com> > Sent: Wednesday, June 22, 2022 10:28 AM > To: Nicolau, Radu <radu.nicolau@intel.com>; Akhil Goyal <gakhil@marvell.com> > Cc: dev@dpdk.org; ndabilpuram@marvell.com > Subject: [PATCH] examples/ipsec-secgw: fix Tx checksum offload flag > > For the inline crypto path set the Tx checksum offload flag > only if the device supports it. > > Fixes: d24471e5786b ("examples/ipsec-secgw: disable Tx checksum for inline") > Cc: ndabilpuram@marvell.com > > Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> > --- Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
> > For the inline crypto path set the Tx checksum offload flag > > only if the device supports it. > > > > Fixes: d24471e5786b ("examples/ipsec-secgw: disable Tx checksum for inline") > > Cc: ndabilpuram@marvell.com > > > > Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> > > --- > Acked-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Akhil Goyal <gakhil@marvell.com> Applied to dpdk-next-crypto Thanks.
diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c index 0b27f11fc0..9b35dfdbef 100644 --- a/examples/ipsec-secgw/sa.c +++ b/examples/ipsec-secgw/sa.c @@ -1841,7 +1841,10 @@ sa_check_offloads(uint16_t port_id, uint64_t *rx_offloads, if (rule->mss) *tx_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO; - *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; + if (dev_info.tx_offload_capa & + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) + *tx_offloads |= + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; } break; default:
For the inline crypto path set the Tx checksum offload flag only if the device supports it. Fixes: d24471e5786b ("examples/ipsec-secgw: disable Tx checksum for inline") Cc: ndabilpuram@marvell.com Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> --- examples/ipsec-secgw/sa.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)