diff mbox series

[2/3] common/sfc_efx/base: report maximum Rx descriptor data count

Message ID 20220812122454.1947322-2-ivan.malov@oktetlabs.ru (mailing list archive)
State Accepted, archived
Delegated to: Andrew Rybchenko
Headers
Series [1/3] common/sfc_efx/base: fix assignment of maximum Tx data count |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Ivan Malov Aug. 12, 2022, 12:24 p.m. UTC 
  Such information is useful to client drivers which deal with
large Rx pool buffers (16-bit wide data count) and thus need
to avoid overflow when setting EF10's 14-bit wide data count.

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
---
 drivers/common/sfc_efx/base/ef10_nic.c  |  1 +
 drivers/common/sfc_efx/base/efx.h       |  1 +
 drivers/common/sfc_efx/base/efx_rx.c    | 12 ++++++++++++
 drivers/common/sfc_efx/base/rhead_nic.c |  4 ++++
 drivers/common/sfc_efx/base/siena_nic.c |  1 +
 5 files changed, 19 insertions(+)
diff mbox series

Patch

diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c
index 7bda778f8b..e1709d1200 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -2233,6 +2233,7 @@  ef10_nic_board_cfg(
 	/* Alignment for WPTR updates */
 	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
 
+	encp->enc_rx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
 	encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_TX_KER_BYTE_CNT);
 	/* No boundary crossing limits */
 	encp->enc_tx_dma_desc_boundary = 0;
diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h
index 95f5fb6bc0..ac26db3e57 100644
--- a/drivers/common/sfc_efx/base/efx.h
+++ b/drivers/common/sfc_efx/base/efx.h
@@ -1587,6 +1587,7 @@  typedef struct efx_nic_cfg_s {
 	/* Number of rx descriptors the hardware requires for a push. */
 	uint32_t		enc_rx_push_align;
 	/* Maximum amount of data in DMA descriptor */
+	uint32_t		enc_rx_dma_desc_size_max;
 	uint32_t		enc_tx_dma_desc_size_max;
 	/*
 	 * Boundary which DMA descriptor data must not cross or 0 if no
diff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c
index 45dc5d6c6d..68f42f5cac 100644
--- a/drivers/common/sfc_efx/base/efx_rx.c
+++ b/drivers/common/sfc_efx/base/efx_rx.c
@@ -978,7 +978,14 @@  efx_rx_qcreate(
 	__in		efx_evq_t *eep,
 	__deref_out	efx_rxq_t **erpp)
 {
+	const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 	efx_rxq_type_data_t type_data;
+	efx_rc_t rc;
+
+	if (buf_size > encp->enc_rx_dma_desc_size_max) {
+		rc = EINVAL;
+		goto fail1;
+	}
 
 	memset(&type_data, 0, sizeof (type_data));
 
@@ -986,6 +993,11 @@  efx_rx_qcreate(
 
 	return efx_rx_qcreate_internal(enp, index, label, type, &type_data,
 	    esmp, ndescs, id, flags, eep, erpp);
+
+fail1:
+	EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+	return (rc);
 }
 
 #if EFSYS_OPT_RX_PACKED_STREAM
diff --git a/drivers/common/sfc_efx/base/rhead_nic.c b/drivers/common/sfc_efx/base/rhead_nic.c
index f2c18c1dcc..eda6c1c4f9 100644
--- a/drivers/common/sfc_efx/base/rhead_nic.c
+++ b/drivers/common/sfc_efx/base/rhead_nic.c
@@ -40,6 +40,10 @@  rhead_board_cfg(
 
 	encp->enc_clk_mult = 1; /* not used for Riverhead */
 
+	EFX_STATIC_ASSERT(MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN == 4);
+	/* Agrees with MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN */
+	encp->enc_rx_dma_desc_size_max = UINT32_MAX;
+
 	/*
 	 * FIXME There are TxSend and TxSeg descriptors on Riverhead.
 	 * TxSeg is bigger than TxSend.
diff --git a/drivers/common/sfc_efx/base/siena_nic.c b/drivers/common/sfc_efx/base/siena_nic.c
index 939551dbf5..9f14faf271 100644
--- a/drivers/common/sfc_efx/base/siena_nic.c
+++ b/drivers/common/sfc_efx/base/siena_nic.c
@@ -146,6 +146,7 @@  siena_board_cfg(
 	 */
 	encp->enc_evq_init_done_ev_supported = B_TRUE;
 
+	encp->enc_rx_dma_desc_size_max = EFX_MASK32(FSF_AZ_RX_KER_BYTE_COUNT);
 	encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
 	/* Fragments must not span 4k boundaries. */
 	encp->enc_tx_dma_desc_boundary = 4096;