From patchwork Mon Aug 15 07:31:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115054 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FA88A00C3; Mon, 15 Aug 2022 01:24:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C147F42C55; Mon, 15 Aug 2022 01:23:00 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 7B1C940146; Mon, 15 Aug 2022 01:22:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660519379; x=1692055379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GjVOipb83x/3xv3i9lhY4Qy6i1R5kr3hiDhgff7Orhs=; b=QlyXIKYUhTiRgS1tyUFQZ+4h0mg+hI3PWa7zE62VLjxkrg+qPQ2FVl3w d6IrxPdf+jvNM3mSOG73mUpWts21xu+9QbwUwgF5+I5NDHamSHNPdOVpD IkM3zEHyUfzoMYPSZWmzEWmODx+hvQij+2ZMK2BHvZp5W9SPQ/iotQMSj 0d7fS7dyRiG7K4ZnICAlOn7oDVD3wi4pjJbR5CgLj5PlIZeeJ8AieutoG SqLAbpxvLUiZcyl3fhkyFXTSVUgR0G09ElxABK7dW5qfMsdhPBn2E3Ova BAAPchm+yaRiTbNBdw2falmAvdJ2O4ZPx9UfW5lAfHDlXLFoLiy8mI8Q5 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="291857958" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="291857958" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:22:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="635283139" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:22:57 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , stable@dpdk.org, Jacob Keller Subject: [PATCH v2 26/70] net/ice/base: fix endian format Date: Mon, 15 Aug 2022 03:31:22 -0400 Message-Id: <20220815073206.2917968-27-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815073206.2917968-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> <20220815073206.2917968-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org A few functions failed to properly convert some values into Little Endian format before sending them to the firmware. This will produce incorrect results when running on a Big Endian platform. Fix this by adding the necessary CPU_TO_LE* macros around the input to firmware. These issues were detected by sparse. Fixes: 0f61c2af88c8 ("net/ice/base: add set/get GPIO helper functions") Cc: stable@dpdk.org Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 57602a31e1..cb06fdf42b 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -4028,7 +4028,7 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm); - desc.datalen = data_size; + desc.datalen = CPU_TO_LE16(data_size); ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params), ICE_NONDMA_TO_NONDMA); cmd->start_address = CPU_TO_LE32(start_address); @@ -5682,7 +5682,7 @@ ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); cmd = &desc.params.read_write_gpio; - cmd->gpio_ctrl_handle = gpio_ctrl_handle; + cmd->gpio_ctrl_handle = CPU_TO_LE16(gpio_ctrl_handle); cmd->gpio_num = pin_idx; cmd->gpio_val = value ? 1 : 0; @@ -5710,7 +5710,7 @@ ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); cmd = &desc.params.read_write_gpio; - cmd->gpio_ctrl_handle = gpio_ctrl_handle; + cmd->gpio_ctrl_handle = CPU_TO_LE16(gpio_ctrl_handle); cmd->gpio_num = pin_idx; status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);