From patchwork Mon Aug 15 07:30:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115030 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA1E6A00C3; Mon, 15 Aug 2022 01:22:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 238894281E; Mon, 15 Aug 2022 01:22:19 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 50DF440150 for ; Mon, 15 Aug 2022 01:22:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660519337; x=1692055337; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AJqw2dRH11a7S77g80A7JC/txMovlXgtA8Oz4wKfWBE=; b=lEE+EHb8uzy9SdH7DRhYOfZZ99sBLluygVh2NOtVcfeV6ICo8FBe2iyd idqCfUbao6/sTv8RE3xTpn11I/rcgSKK0H6XN6xr0zE0f8VyabLGnwoZv EyCy09rAIkewiXgKS5MjbU3DAsdnP0UPi/X0Ghbp3d3Xn9N8bqWm8bkiR CkZa1xIg8BUbsdDm5+rVfGGciM361GF2RVCWllgW+qGIaeFiww8BSfQZI 9h4qihNqlkq/vq8fjgxQRvTXHe+PUcJ6HSAWsmIOynsy/PYfDtEdxqub7 7K0hnJTMiqO1tUVIGyZH8tkjrY4/o03yYR8f0C2CvR2r08ZJWv4JZauEC A==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="291857911" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="291857911" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:22:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="635282982" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:22:15 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Paul Greenwalt Subject: [PATCH v2 02/70] net/ice/base: get NVM CSS Header length from the CSS Header Date: Mon, 15 Aug 2022 03:30:58 -0400 Message-Id: <20220815073206.2917968-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815073206.2917968-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> <20220815073206.2917968-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The CSS Header length is defined as ICE_CSS_HEADER_LENGTH. To support changes in CSS Header length, calculate the CSS Header length from the NVM CSS Header length field plus the Authentication Header length. Signed-off-by: Paul Greenwalt Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_nvm.c | 61 +++++++++++++++++++++++++++++---- drivers/net/ice/base/ice_type.h | 12 +++---- 2 files changed, 59 insertions(+), 14 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 7860006206..ad2496e873 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -350,6 +350,42 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1 return status; } +/** + * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header + * @hw: pointer to the HW struct + * @bank: whether to read from the active or inactive flash bank + * @hdr_len: storage for header length in words + * + * Read the CSS header length from the NVM CSS header and add the Authentication + * header size, and then convert to words. + */ +static enum ice_status +ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank, + u32 *hdr_len) +{ + u16 hdr_len_l, hdr_len_h; + enum ice_status status; + u32 hdr_len_dword; + + status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L, + &hdr_len_l); + if (status) + return status; + + status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H, + &hdr_len_h); + if (status) + return status; + + /* CSS header length is in DWORD, so convert to words and add + * authentication header size + */ + hdr_len_dword = hdr_len_h << 16 | hdr_len_l; + *hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN; + + return ICE_SUCCESS; +} + /** * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank * @hw: pointer to the HW structure @@ -363,7 +399,16 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1 static enum ice_status ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) { - return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data); + enum ice_status status; + u32 hdr_len; + + status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len); + if (status) + return status; + + hdr_len = ROUND_UP(hdr_len, 32); + + return ice_read_nvm_module(hw, bank, hdr_len + offset, data); } /** @@ -633,22 +678,26 @@ enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info */ static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev) { + u32 orom_size_word = hw->flash.banks.orom_size / 2; enum ice_status status; u16 srev_l, srev_h; u32 css_start; + u32 hdr_len; - if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) { + status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len); + if (status) + return status; + + if (orom_size_word < hdr_len) { ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n", hw->flash.banks.orom_size); return ICE_ERR_CFG; } /* calculate how far into the Option ROM the CSS header starts. Note - * that ice_read_orom_module takes a word offset so we need to - * divide by 2 here. + * that ice_read_orom_module takes a word offset */ - css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2; - + css_start = orom_size_word - hdr_len; status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l); if (status) return status; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index d81984633a..d4d0cab089 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1419,17 +1419,13 @@ struct ice_aq_get_set_rss_lut_params { #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118 /* CSS Header words */ +#define ICE_NVM_CSS_HDR_LEN_L 0x02 +#define ICE_NVM_CSS_HDR_LEN_H 0x03 #define ICE_NVM_CSS_SREV_L 0x14 #define ICE_NVM_CSS_SREV_H 0x15 -/* Length of CSS header section in words */ -#define ICE_CSS_HEADER_LENGTH 330 - -/* Offset of Shadow RAM copy in the NVM bank area. */ -#define ICE_NVM_SR_COPY_WORD_OFFSET ROUND_UP(ICE_CSS_HEADER_LENGTH, 32) - -/* Size in bytes of Option ROM trailer */ -#define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) +/* Length of Authentication header section in words */ +#define ICE_NVM_AUTH_HEADER_LEN 0x08 /* The Link Topology Netlist section is stored as a series of words. It is * stored in the NVM as a TLV, with the first two words containing the type