From patchwork Mon Aug 15 07:31:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115060 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B1436A00C3; Mon, 15 Aug 2022 01:25:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ABFFD42C77; Mon, 15 Aug 2022 01:23:11 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 5A27242BB0 for ; Mon, 15 Aug 2022 01:23:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660519389; x=1692055389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NIikhjzfRgwaN8T9W4ru0uSla5R+fMgppL38dPMU+10=; b=lRtLXGMn+GI8zBWvaawzXfbhW4K94I7k8KaoEb8Ke/piUcxvTiSVHcS8 yP0Hllqm1UGSVIp3FjCTaDaQcpdrA/VwR72N/DxMyO2l0aNIXoE7s8YjF rVvJXJbiXna7KDcrj9FKb0zp1/lzsAmkV2UWSz6luRTT/2MKVPy/RJKgV nY6WfHX+YAsI31alv3c+RCyIpz7YQ7Ybc8Hc3Di0bKypsaIYIAcJCngrZ qv2pWdAowBTDVtwZVR/f9onWcIJYiwaN6ERs9aL4Ab+ALYWM7Y4zEWEgc d1w4JjDlnlpGJg4aFUMYRaMcARwVrLJbE4tA56KhPiKR+lyIjUu5xy5bW g==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="291857970" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="291857970" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:23:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="635283170" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:23:07 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Karol Kolacinski Subject: [PATCH v2 32/70] net/ice/base: change PHY/QUAD/ports definitions Date: Mon, 15 Aug 2022 03:31:28 -0400 Message-Id: <20220815073206.2917968-33-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815073206.2917968-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> <20220815073206.2917968-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rename PHY/QUAD/ports definitions to reflect the correct HW specification. Signed-off-by: Karol Kolacinski Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.c | 45 ++++++++++++++++--------------- drivers/net/ice/base/ice_type.h | 14 +++++----- 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 3df0915cd3..7ed420be8e 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1794,9 +1794,9 @@ ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset) { int phy_port, phy, quadtype; - phy_port = port % ICE_PORTS_PER_PHY; - phy = port / ICE_PORTS_PER_PHY; - quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE; + phy_port = port % ICE_PORTS_PER_PHY_E822; + phy = port / ICE_PORTS_PER_PHY_E822; + quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_QUADS_PER_PHY_E822; if (quadtype == 0) { msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); @@ -2184,20 +2184,25 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) * Fill a message buffer for accessing a register in a quad shared between * multiple PHYs. */ -static void +static enum ice_status ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset) { u32 addr; + if (quad >= ICE_MAX_QUAD) + return ICE_ERR_PARAM; + msg->dest_dev = rmn_0; - if ((quad % ICE_NUM_QUAD_TYPE) == 0) + if ((quad % ICE_QUADS_PER_PHY_E822) == 0) addr = Q_0_BASE + offset; else addr = Q_1_BASE + offset; msg->msg_addr_low = ICE_LO_WORD(addr); msg->msg_addr_high = ICE_HI_WORD(addr); + + return ICE_SUCCESS; } /** @@ -2218,22 +2223,21 @@ ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val, struct ice_sbq_msg_input msg = {0}; enum ice_status status; - if (quad >= ICE_MAX_QUAD) - return ICE_ERR_PARAM; + status = ice_fill_quad_msg_e822(&msg, quad, offset); + if (status) + goto exit_err; - ice_fill_quad_msg_e822(&msg, quad, offset); msg.opcode = ice_sbq_msg_rd; status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); - if (status) { +exit_err: + if (status) ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n", status); - return status; - } - - *val = msg.data; + else + *val = msg.data; - return ICE_SUCCESS; + return status; } enum ice_status @@ -2260,21 +2264,20 @@ ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val, struct ice_sbq_msg_input msg = {0}; enum ice_status status; - if (quad >= ICE_MAX_QUAD) - return ICE_ERR_PARAM; + status = ice_fill_quad_msg_e822(&msg, quad, offset); + if (status) + goto exit_err; - ice_fill_quad_msg_e822(&msg, quad, offset); msg.opcode = ice_sbq_msg_wr; msg.data = val; status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq); - if (status) { +exit_err: + if (status) ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy, status %d\n", status); - return status; - } - return ICE_SUCCESS; + return status; } enum ice_status diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index b8be0d948a..5c7cc06e0c 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1191,13 +1191,13 @@ struct ice_hw { /* true if VSIs can share unicast MAC addr */ u8 umac_shared; -#define ICE_PHY_PER_NAC 1 -#define ICE_MAX_QUAD 2 -#define ICE_NUM_QUAD_TYPE 2 -#define ICE_PORTS_PER_QUAD 4 -#define ICE_PHY_0_LAST_QUAD 1 -#define ICE_PORTS_PER_PHY 8 -#define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY +#define ICE_PHY_PER_NAC_E822 1 +#define ICE_MAX_QUAD 2 +#define ICE_QUADS_PER_PHY_E822 2 +#define ICE_PORTS_PER_PHY_E822 8 +#define ICE_PORTS_PER_QUAD 4 +#define ICE_PORTS_PER_PHY_E810 4 +#define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD) /* bitmap of enabled logical ports */ u32 ena_lports;