From patchwork Mon Aug 15 07:31:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 115036 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC7CFA00C3; Mon, 15 Aug 2022 01:23:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 80C2242BA6; Mon, 15 Aug 2022 01:22:28 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 5FFD142B8B for ; Mon, 15 Aug 2022 01:22:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660519347; x=1692055347; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OkDcUgBt7kmIijnjRcsttJh1i/L+KsrL94Q5D5ZPSCc=; b=Xz5OxmG8QB3afSz8dwv6gwBjnbDtgi0KeZ5NWGToKCZO0EFuR0gsSsBu csi29vLK0J8zRiKXmcYSR0lB9VA6cedFOas2LuquQT0zH109rOngcuBRD y+Cr1VkNawK4OMKdReU9GioG65jcBUsQUvCKJQ7+Gv9MXzV+jhYWp7PMj ETGki+KC6a3qFBitTwhd5y5IzJeWzWEY2knq7ashcGaxTgjLCI7apMMRy AxZS6If3dLAc5yNp0Fl4QbwScJN5BTsNNIhvRh+4EddPHVKY60j9iJ3j1 PhnnvOGDxO0fxl8oAlISI9DKwdYsVgd2n1qTI7sJGlTShrwPzEbwBdO4G A==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="291857924" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="291857924" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:22:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="635283011" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:22:25 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Jie Wang Subject: [PATCH v2 08/70] net/ice/base: support VXLAN and GRE for RSS Date: Mon, 15 Aug 2022 03:31:04 -0400 Message-Id: <20220815073206.2917968-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815073206.2917968-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> <20220815073206.2917968-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add RSS of inner headers for VXLAN tunnel packet. Add packet types for packets with outer IPv4/IPv6 header support GRE and VXLAN tunnel packet. Following rules can use new packet types: - eth / ipv4(6) / udp / vxlan / ipv4(6) - eth / ipv4(6) / udp / vxlan / ipv4(6) / tcp - eth / ipv4(6) / udp / vxlan / ipv4(6) / udp - eth / ipv4(6) / gre / ipv4(6) - eth / ipv4(6) / gre / ipv4(6) / tcp - eth / ipv4(6) / gre / ipv4(6) / udp Signed-off-by: Jie Wang Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index d7eecc0d54..bdb584c7f5 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -262,7 +262,7 @@ static const u32 ice_ptypes_macvlan_il[] = { * does NOT include IPV4 other PTYPEs */ static const u32 ice_ptypes_ipv4_ofos[] = { - 0x1D800000, 0x24000800, 0x00000000, 0x00000000, + 0x1D800000, 0xBFBF7800, 0x000001DF, 0x00000000, 0x00000000, 0x00000155, 0x00000000, 0x00000000, 0x00000000, 0x000FC000, 0x000002A0, 0x00100000, 0x00001500, 0x00000000, 0x00000000, 0x00000000, @@ -316,8 +316,8 @@ static const u32 ice_ptypes_ipv6_ofos[] = { * includes IPV6 other PTYPEs */ static const u32 ice_ptypes_ipv6_ofos_all[] = { - 0x00000000, 0x00000000, 0x76000000, 0x1EFDE000, - 0x00000000, 0x000002AA, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x76000000, 0xFEFDE000, + 0x0000077E, 0x000002AA, 0x00000000, 0x00000000, 0x00000000, 0x03F00000, 0x7C1F0540, 0x00000206, 0xFC002000, 0x0000003F, 0xBC000000, 0x0002FBEF, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -985,8 +985,9 @@ struct ice_flow_prof_params { ICE_FLOW_SEG_HDR_PFCP_SESSION | ICE_FLOW_SEG_HDR_L2TPV3 | \ ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \ ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \ + ICE_FLOW_SEG_HDR_VXLAN | ICE_FLOW_SEG_HDR_GRE | \ ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \ - ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE) + ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP) #define ICE_FLOW_SEG_HDRS_L2_MASK \ (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)