From patchwork Wed Aug 17 06:08:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 115192 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23F07A0032; Wed, 17 Aug 2022 09:18:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E77741147; Wed, 17 Aug 2022 09:17:53 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id CF08C41147 for ; Wed, 17 Aug 2022 09:17:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660720672; x=1692256672; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=EsNOrq4wcI7GlcmJmGjEo/vEqa9177YGO9Xn07Dpnzs=; b=BKWgxYRjDaui7SEKq0s0hz6+EIFOY6mYPN51vJEk5Rnxj8EOmXBJJHcv 9HzqL/mrTi9Yk+P3o2YhpsrgaXKcG1jmkAdYz9hRxqWQNoUoqOdjscP1c Zod1Vv3EK5/7+tye+aghduUL+RypZZm6Uv6u+mXy0pdZu69xZbzvzwIS2 8gwsEKUVB08PoyC2vxct8zH1R8MzFbhcgvPH/rGvSUWPSmjtWEIkOeqfo B/Z8wjPb3pVP9ADPjQ00uXzsDFp84tmq54NffeyK1hEgS3GyAm/ZnMqd6 hi3zgLareN/SuX/6upNb7t6zCrHdZaBzDyC2uh22jWaA/TbojFEz9xxL/ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10441"; a="356421128" X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="356421128" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 00:17:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="667485799" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga008.fm.intel.com with ESMTP; 17 Aug 2022 00:17:50 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, Arek Kusztal Subject: [PATCH 3/4] crypto/qat: add SM4 encryption algorithm Date: Wed, 17 Aug 2022 07:08:55 +0100 Message-Id: <20220817060856.78582-4-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20220817060856.78582-1-arkadiuszx.kusztal@intel.com> References: <20220817060856.78582-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Added SM4 encryption algorithms. Supported modes: ECB, CBC, CTR. Signed-off-by: Arek Kusztal --- doc/guides/cryptodevs/features/qat.ini | 3 +++ doc/guides/rel_notes/release_22_11.rst | 4 ++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 9 +++++++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 9 +++++++++ drivers/crypto/qat/qat_sym_session.c | 12 ++++++++++++ 5 files changed, 37 insertions(+) diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini index b9755a757e..edabc030d7 100644 --- a/doc/guides/cryptodevs/features/qat.ini +++ b/doc/guides/cryptodevs/features/qat.ini @@ -40,6 +40,9 @@ KASUMI F8 = Y AES DOCSIS BPI = Y DES DOCSIS BPI = Y ZUC EEA3 = Y +SM4 ECB = Y +SM4 CBC = Y +SM4 CTR = Y ; ; Supported authentication algorithms of the 'qat' crypto driver. ; diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst index 0609652b07..c6638ded82 100644 --- a/doc/guides/rel_notes/release_22_11.rst +++ b/doc/guides/rel_notes/release_22_11.rst @@ -64,6 +64,10 @@ New Features Added SM3 hash algorithm to the Cryptodev API. +* **Updated the Intel QuickAssist Technology (QAT) symmetric crypto PMD.** + + Added SM4 encryption algorithm to the QAT PMD. + Supported modes are ECB, CBC and CTR. Removed Items ------------- diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 2d5f10aeac..d1285cdbd4 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -131,6 +131,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = { CAP_RNG(key_size, 32, 32, 0), CAP_RNG(digest_size, 16, 16, 0), CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)), + QAT_SYM_CIPHER_CAP(SM4_ECB, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)), + QAT_SYM_CIPHER_CAP(SM4_CBC, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), + QAT_SYM_CIPHER_CAP(SM4_CTR, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index a9457d9278..efbbbda4b6 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -91,6 +91,15 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = { CAP_RNG(key_size, 32, 32, 0), CAP_RNG(digest_size, 16, 16, 0), CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)), + QAT_SYM_CIPHER_CAP(SM4_ECB, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 0, 0, 0)), + QAT_SYM_CIPHER_CAP(SM4_CBC, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), + QAT_SYM_CIPHER_CAP(SM4_CTR, + CAP_SET(block_size, 16), + CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index b30396487e..f4e0faa8e1 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -432,6 +432,18 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_XTS_MODE; break; + case RTE_CRYPTO_CIPHER_SM4_ECB: + session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4; + session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE; + break; + case RTE_CRYPTO_CIPHER_SM4_CBC: + session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4; + session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE; + break; + case RTE_CRYPTO_CIPHER_SM4_CTR: + session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_SM4; + session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; + break; case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_AES_ECB: case RTE_CRYPTO_CIPHER_AES_F8: