diff mbox series

[v2,28/31] net/cnxk: Add support for crypto auth alg MD5

Message ID	20220905133228.818616-28-ndabilpuram@marvell.com (mailing list archive)
State	Superseded, archived
Delegated to:	Jerin Jacob
Headers	From: Nithin Dabilpuram <ndabilpuram@marvell.com> To: Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com> CC: <jerinj@marvell.com>, <dev@dpdk.org>, Vidya Sagar Velumuri <vvelumuri@marvell.com> Subject: [PATCH v2 28/31] net/cnxk: Add support for crypto auth alg MD5 Date: Mon, 5 Sep 2022 19:02:25 +0530 Message-ID: <20220905133228.818616-28-ndabilpuram@marvell.com> In-Reply-To: <20220905133228.818616-1-ndabilpuram@marvell.com> References: <20220809184908.24030-1-ndabilpuram@marvell.com> <20220905133228.818616-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	[v2,01/31] cnxk/net: add fc check in vector event Tx path \| [v2,01/31] cnxk/net: add fc check in vector event Tx path [v2,02/31] common/cnxk: fix part value for cn10k [v2,03/31] common/cnxk: add cn10ka A1 platform [v2,04/31] common/cnxk: update inbound inline IPsec config mailbox [v2,05/31] net/cnxk: fix missing fc wait for outbound path in vec mode [v2,06/31] common/cnxk: limit meta aura workaround to CN10K A0 [v2,07/31] common/cnxk: delay inline device RQ enable to dev start [v2,08/31] common/cnxk: reserve aura zero on cn10ka NPA [v2,09/31] common/cnxk: add support to set NPA buf type [v2,10/31] common/cnxk: update attributes to pools used by NIX [v2,11/31] common/cnxk: support zero aura for inline inbound meta [v2,12/31] net/cnxk: support for zero aura for inline meta [v2,13/31] common/cnxk: avoid the use of platform specific APIs [v2,14/31] net/cnxk: use full context IPsec structures in fp [v2,15/31] net/cnxk: add crypto capabilities for HMAC-SHA2 [v2,16/31] common/cnxk: enable aging on CN10K platform [v2,17/31] common/cnxk: updated shaper profile with red algorithm [v2,18/31] common/cnxk: add 98xx A1 platform [v2,19/31] net/cnxk: enable additional ciphers for inline [v2,20/31] net/cnxk: enable 3des-cbc cipher capability [v2,21/31] net/cnxk: skip PFC configuration on LBK [v2,22/31] common/cnxk: add support for CPT second pass [v2,23/31] common/cnxk: add CQ limit associated with SQ [v2,24/31] common/cnxk: support Tx compl event via RQ to CQ mapping [v2,25/31] event/cnxk: wait for CPT fc on wqe path [v2,26/31] net/cnxk: limit port specific SA table size [v2,27/31] net/cnxk: add support for crypto cipher DES-CBC [v2,28/31] net/cnxk: Add support for crypto auth alg MD5 [v2,29/31] net/cnxk: enable esn and antireplay support [v2,30/31] common/cnxk: dump device basic info to file [v2,31/31] net/cnxk: dumps device private information

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Nithin Dabilpuram Sept. 5, 2022, 1:32 p.m. UTC

  From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Add support for MD5 auth algo for security offload in inline mode.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c |  4 ++++
 drivers/net/cnxk/cn9k_ethdev_sec.c  | 20 ++++++++++++++++++++
 2 files changed, 24 insertions(+)

diff mbox series

Patch

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index f25df54254..55382d3129 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -852,6 +852,7 @@  cnxk_ipsec_icvlen_get(enum rte_crypto_cipher_algorithm c_algo,
 	case RTE_CRYPTO_AUTH_NULL:
 		icv = 0;
 		break;
+	case RTE_CRYPTO_AUTH_MD5_HMAC:
 	case RTE_CRYPTO_AUTH_SHA1_HMAC:
 		icv = 12;
 		break;
@@ -1208,6 +1209,7 @@  cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec,
 		ctx_len = offsetof(struct roc_ie_on_outb_sa, aes_gcm.template);
 	} else {
 		switch (ctl->auth_type) {
+		case ROC_IE_ON_SA_AUTH_MD5:
 		case ROC_IE_ON_SA_AUTH_SHA1:
 			template = &out_sa->sha1.template;
 			ctx_len = offsetof(struct roc_ie_on_outb_sa,
@@ -1306,6 +1308,7 @@  cnxk_on_ipsec_outb_sa_create(struct rte_security_ipsec_xform *ipsec,
 		case RTE_CRYPTO_AUTH_AES_GMAC:
 		case RTE_CRYPTO_AUTH_NULL:
 			break;
+		case RTE_CRYPTO_AUTH_MD5_HMAC:
 		case RTE_CRYPTO_AUTH_SHA1_HMAC:
 			memcpy(out_sa->sha1.hmac_key, auth_key, auth_key_len);
 			break;
@@ -1354,6 +1357,7 @@  cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec,
 		switch (auth_xform->auth.algo) {
 		case RTE_CRYPTO_AUTH_NULL:
 			break;
+		case RTE_CRYPTO_AUTH_MD5_HMAC:
 		case RTE_CRYPTO_AUTH_SHA1_HMAC:
 			memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key,
 			       auth_key_len);
diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c
index aa9aa29b4a..90cb1d252d 100644
--- a/drivers/net/cnxk/cn9k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c
@@ -185,6 +185,26 @@  static struct rte_cryptodev_capabilities cn9k_eth_sec_crypto_caps[] = {
 			}, }
 		}, }
 	},
+	{	/* MD5 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				},
+			}, }
+		}, }
+	},
 	{	/* SHA1 HMAC */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 		{.sym = {