[v3] config/arm: add PHYTIUM tys2500

Message ID 20221011111433.690-1-luzhipeng@cestc.cn (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series [v3] config/arm: add PHYTIUM tys2500 |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

luzhipeng Oct. 11, 2022, 11:14 a.m. UTC
  From: Zhipeng Lu <luzhipeng@cestc.cn>

Here adds configs for PHYTIUM server.

Signed-off-by: Zhipeng Lu <luzhipeng@cestc.cn>
---
v3:
* fix typos
* fix signed-off-by format
v2:
* add ccache for cross build
* rename fts2500 to tys2500 and modify the corresponding code

 config/arm/arm64_tys2500_linux_gcc | 16 ++++++++++++++++
 config/arm/meson.build             | 26 +++++++++++++++++++++++---
 2 files changed, 39 insertions(+), 3 deletions(-)
 create mode 100644 config/arm/arm64_tys2500_linux_gcc
  

Comments

Thomas Monjalon Oct. 26, 2022, 3:40 p.m. UTC | #1
11/10/2022 13:14, luzhipeng:
> From: Zhipeng Lu <luzhipeng@cestc.cn>
> 
> Here adds configs for PHYTIUM server.
> 
> Signed-off-by: Zhipeng Lu <luzhipeng@cestc.cn>

Applied, thanks.
  

Patch

diff --git a/config/arm/arm64_tys2500_linux_gcc b/config/arm/arm64_tys2500_linux_gcc
new file mode 100644
index 0000000000..fce85fb0d8
--- /dev/null
+++ b/config/arm/arm64_tys2500_linux_gcc
@@ -0,0 +1,16 @@ 
+[binaries]
+c = ['ccache', 'aarch64-linux-gnu-gcc']
+cpp = ['ccache', 'aarch64-linux-gnu-g++']
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+platform = 'tys2500'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index b7162d516d..6442ec9596 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -213,13 +213,24 @@  implementer_phytium = {
         ['RTE_MACHINE', '"armv8a"'],
         ['RTE_USE_C11_MEM_MODEL', true],
         ['RTE_CACHE_LINE_SIZE', 64],
-        ['RTE_MAX_LCORE', 64],
-        ['RTE_MAX_NUMA_NODES', 8]
     ],
     'part_number_config': {
         '0x662': {
-            'machine_args': ['-march=armv8-a+crc'],
+            'march': 'armv8-a',
+            'march_features': ['crc'],
+            'flags': [
+                ['RTE_MAX_LCORE', 64],
+                ['RTE_MAX_NUMA_NODES', 8]
+             ]
         },
+       '0x663': {
+            'march': 'armv8-a',
+            'march_features': ['crc'],
+            'flags': [
+                ['RTE_MAX_LCORE', 256],
+                ['RTE_MAX_NUMA_NODES', 32]
+            ]
+        }
     }
 }
 
@@ -339,6 +350,13 @@  soc_ft2000plus = {
     'numa': true
 }
 
+soc_tys2500 = {
+    'description': 'Phytium TengYun S2500',
+    'implementer': '0x70',
+    'part_number': '0x663',
+    'numa': true
+}
+
 soc_graviton2 = {
     'description': 'AWS Graviton2',
     'implementer': '0x41',
@@ -436,6 +454,7 @@  cn10k:           Marvell OCTEON 10
 dpaa:            NXP DPAA
 emag:            Ampere eMAG
 ft2000plus:      Phytium FT-2000+
+tys2500:         Phytium TengYun S2500
 graviton2:       AWS Graviton2
 graviton3:       AWS Graviton3
 kunpeng920:      HiSilicon Kunpeng 920
@@ -461,6 +480,7 @@  socs = {
     'dpaa': soc_dpaa,
     'emag': soc_emag,
     'ft2000plus': soc_ft2000plus,
+    'tys2500': soc_tys2500,
     'graviton2': soc_graviton2,
     'graviton3': soc_graviton3,
     'kunpeng920': soc_kunpeng920,