diff mbox series

[05/13] common/cnxk: fix RQ mask config for cn10kb chip

Message ID	20221011120135.45846-5-ndabilpuram@marvell.com (mailing list archive)
State	Changes Requested, archived
Delegated to:	Jerin Jacob
Headers	From: Nithin Dabilpuram <ndabilpuram@marvell.com> To: Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao <skoteshwar@marvell.com> CC: <jerinj@marvell.com>, <dev@dpdk.org> Subject: [PATCH 05/13] common/cnxk: fix RQ mask config for cn10kb chip Date: Tue, 11 Oct 2022 17:31:27 +0530 Message-ID: <20221011120135.45846-5-ndabilpuram@marvell.com> In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	[01/13] common/cnxk: set MTU size on SDP based on SoC type \| [01/13] common/cnxk: set MTU size on SDP based on SoC type [02/13] common/cnxk: add devargs for soft expiry poll frequency [03/13] net/cnxk: fix later skip to include mbuf priv [04/13] net/cnxk: add use nixtx offset for cn10kb [05/13] common/cnxk: fix RQ mask config for cn10kb chip [06/13] common/cnxk: fix schedule weight update [07/13] common/cnxk: sync NIX HW info mbox structure with kernel [08/13] common/cnxk: revert VF root weight [09/13] common/cnxk: set hysteresis bit to one [10/13] net/cnxk: handle SA soft packet and byte expiry events [11/13] common/cnxk: sync mailbox for channel and bpid map [12/13] net/cnxk: remove unnecessary dptr update [13/13] net/cnxk: remove duplicate mempool debug checks

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Nithin Dabilpuram Oct. 11, 2022, 12:01 p.m. UTC

  RQ mask config needs to enable SPB_ENA in order for Zero for
being able to override it with Meta aura.

Also fix flow control config to catch invalid rxchan config
errors.

Fixes: ddf955d3917e ("common/cnxk: support CPT second pass")
Fixes: da57d4589a6f ("common/cnxk: support NIX flow control")

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_fc.c  |  4 ++-
 drivers/common/cnxk/roc_nix_inl.c | 43 +++++++++++++++++--------------
 2 files changed, 26 insertions(+), 21 deletions(-)

diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index f4cfa11c0f..033e17a4bf 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -52,8 +52,10 @@  nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable)
 		req->bpid_per_chan = true;
 
 		rc = mbox_process_msg(mbox, (void *)&rsp);
-		if (rc || (req->chan_cnt != rsp->chan_cnt))
+		if (rc || (req->chan_cnt != rsp->chan_cnt)) {
+			rc = -EIO;
 			goto exit;
+		}
 
 		nix->chan_cnt = rsp->chan_cnt;
 		for (i = 0; i < rsp->chan_cnt; i++)
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 213d71e684..0da097c9e9 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -454,27 +454,29 @@  nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 	msk_req->rq_set.lpb_drop_ena = 0;
 	msk_req->rq_set.spb_drop_ena = 0;
 	msk_req->rq_set.xqe_drop_ena = 0;
+	msk_req->rq_set.spb_ena = 1;
 
-	msk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis);
-	msk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis);
-	msk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis);
+	msk_req->rq_mask.len_ol3_dis = 0;
+	msk_req->rq_mask.len_ol4_dis = 0;
+	msk_req->rq_mask.len_il3_dis = 0;
 
-	msk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis);
-	msk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis);
-	msk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis);
+	msk_req->rq_mask.len_il4_dis = 0;
+	msk_req->rq_mask.csum_ol4_dis = 0;
+	msk_req->rq_mask.csum_il4_dis = 0;
 
-	msk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis);
-	msk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis);
-	msk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis);
+	msk_req->rq_mask.lenerr_dis = 0;
+	msk_req->rq_mask.port_ol4_dis = 0;
+	msk_req->rq_mask.port_il4_dis = 0;
 
-	msk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena);
-	msk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena);
-	msk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena);
+	msk_req->rq_mask.lpb_drop_ena = 0;
+	msk_req->rq_mask.spb_drop_ena = 0;
+	msk_req->rq_mask.xqe_drop_ena = 0;
+	msk_req->rq_mask.spb_ena = 0;
 
 	aura_handle = roc_npa_zero_aura_handle();
 	msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);
 	msk_req->ipsec_cfg1.rq_mask_enable = enable;
-	msk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz;
+	msk_req->ipsec_cfg1.spb_cpt_sizem1 = (inl_cfg->buf_sz >> 7) - 1;
 	msk_req->ipsec_cfg1.spb_cpt_enable = enable;
 
 	return mbox_process(mbox);
@@ -544,13 +546,6 @@  roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 		idev->inl_cfg.refs++;
 	}
 
-	if (roc_model_is_cn10kb_a0()) {
-		rc = nix_inl_rq_mask_cfg(roc_nix, true);
-		if (rc) {
-			plt_err("Failed to get rq mask rc=%d", rc);
-			return rc;
-		}
-	}
 	nix->inl_inb_ena = true;
 	return 0;
 }
@@ -1043,6 +1038,14 @@  roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable)
 	if (!idev)
 		return -EFAULT;
 
+	if (roc_model_is_cn10kb_a0()) {
+		rc = nix_inl_rq_mask_cfg(roc_nix, true);
+		if (rc) {
+			plt_err("Failed to get rq mask rc=%d", rc);
+			return rc;
+		}
+	}
+
 	if (nix->inb_inl_dev) {
 		if (!inl_rq || !idev->nix_inl_dev)
 			return -EFAULT;