From patchwork Thu Oct 13 11:41:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118148 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D798AA00C3; Thu, 13 Oct 2022 13:43:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 894D442F3A; Thu, 13 Oct 2022 13:42:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 56E5742F37 for ; Thu, 13 Oct 2022 13:42:31 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29D9I7xk010292 for ; Thu, 13 Oct 2022 04:42:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=f5vrnSadAnc9Cg8X73VyVLGsK7alxFdJRwy8WBVetcY=; b=h4LOn6ZvAhPu3/bMUrqINyTVlcMaQMhghN9DAXqqzsv/3AYMSCHsSERaa5yPOQoTOM2l XBvskQEhgEGUVBra1Eg5zUEIl+RShdnbcZUbzzwc5nzzi9N7cwkyWgOeRUZ7RZzXCVZZ Sjq4awmU4sZET7fMlKz+Og6r/ZZwxnbbqsKtD4PzRwMlHoaMENP6bY7v05bpGCEp7dul roGJYhDlqzR2GUAWmRSxjV1rHlp7CZMn00sGRUY9dJY8ZDXPv2kgLfvUUzY9xhkd8pPQ 1AWmL4dS9K0C+iHcTFYRbW05uO0Q3LvyWWZ3XefTMnurw1NHSzg7VbxMWWIO9oUcRrM5 FQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k6fwv8eff-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 04:42:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 04:42:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 04:42:28 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 86AA83F703F; Thu, 13 Oct 2022 04:42:26 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v2 10/13] common/cnxk: sync mailbox for channel and bpid map Date: Thu, 13 Oct 2022 17:11:53 +0530 Message-ID: <20221013114156.996517-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013114156.996517-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221013114156.996517-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: MbnDtoPfAZLi_LcWWy9yWx0vN290SFjk X-Proofpoint-ORIG-GUID: MbnDtoPfAZLi_LcWWy9yWx0vN290SFjk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-13_08,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori As per recent change in Linux-5.4.x, mailbox is updated to configure mapping between channel and BPID. Due to mbox mismatch, PFC was broken. Patch syncs mailbox definition for the same. Also fixes the PFC configuration issues. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_mbox.h | 6 +++--- drivers/common/cnxk/roc_nix.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index e8d4ae283d..d47808e5ef 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1164,10 +1164,10 @@ struct nix_bp_cfg_req { /* bpid_per_chan = 1 assigns separate bp id for each channel */ }; -/* PF can be mapped to either CGX or LBK interface, - * so maximum 64 channels are possible. +/* PF can be mapped to either CGX or LBK or SDP interface, + * so maximum 256 channels are possible. */ -#define NIX_MAX_CHAN 64 +#define NIX_MAX_CHAN 256 #define NIX_CGX_MAX_CHAN 16 #define NIX_LBK_MAX_CHAN 1 struct nix_bp_cfg_rsp { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 6636ee52c1..6654a2df78 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -436,7 +436,7 @@ struct roc_nix { bool rx_ptp_ena; uint16_t cints; -#define ROC_NIX_MEM_SZ (6 * 1024) +#define ROC_NIX_MEM_SZ (6 * 1056) uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned;