[v2,08/13] common/cnxk: set hysteresis bit to one

Message ID 20221013114156.996517-8-ndabilpuram@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Jerin Jacob
Headers
Series [v2,01/13] common/cnxk: set MTU size on SDP based on SoC type |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Oct. 13, 2022, 11:41 a.m. UTC
  From: Satha Rao <skoteshwar@marvell.com>

Setting non zero FC_HYST_BITS to reduce mesh traffic on HW.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix_queue.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Patch

diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 7318f26b57..1cb1fd2101 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -940,7 +940,7 @@  sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
 	else
 		aura.fc_stype = 0x3; /* STSTP */
 	aura.fc_addr = (uint64_t)sq->fc;
-	aura.fc_hyst_bits = 0; /* Store count on all updates */
+	aura.fc_hyst_bits = 1; /* Store count on all updates */
 	rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura,
 				 &pool, 0);
 	if (rc)