From patchwork Mon Nov 28 09:54:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 120203 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 886EAA00C3; Mon, 28 Nov 2022 10:55:34 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF00542D25; Mon, 28 Nov 2022 10:55:12 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B3CFF42D35 for ; Mon, 28 Nov 2022 10:55:10 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AS5jW1M026598 for ; Mon, 28 Nov 2022 01:55:09 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=w12dMbtgdVQ2fIThJq3a56iWtBKrnIGoYgbNPXav3/k=; b=RLXyFi0Vozys1lArmp27Zi9Y0UPYgf9KTSOj57RvjlPrLw+XlsopJnmrhUxEMsLuRxi7 /IU78oxaTneMPHW5/50+q6gVSpnGLyGMrak4430V44YMITz43LM64Ktkm+WQIL00hM3P dmIMEjuNrCPH+p5oKfTPkWdM1zpr7L9Kq8ld4G6RHLYOO28rUWiAfIxUM7oIUa31Zczm 1TzJjtdygCeB4yJHIRC2hgeIb3j4T28/spnBdoTjPMkG30+PiYNopWBPNm6mjWRgJjdx eq36kUtNnFyWKX/bkO+lO+Z6gzREVYEp3YRpabi498gK9IMuQrokXX0+18aELyWLWXCr 1g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3m4q3srsfu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 28 Nov 2022 01:55:09 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 28 Nov 2022 01:55:08 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 28 Nov 2022 01:55:08 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0D8B63F704A; Mon, 28 Nov 2022 01:55:05 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 07/11] net/cnxk: add late backpressure support for cn10kb Date: Mon, 28 Nov 2022 15:24:38 +0530 Message-ID: <20221128095442.3185112-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128095442.3185112-1-ndabilpuram@marvell.com> References: <20221128095442.3185112-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7w6g75PntvcudKSAcGT2POz_ViCvTcme X-Proofpoint-GUID: 7w6g75PntvcudKSAcGT2POz_ViCvTcme X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-28_07,2022-11-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add late backpressure support for cn10kb and set it up to backpressure CPT. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/hw/nix.h | 18 ++++++++++++------ drivers/common/cnxk/roc_model.h | 6 ++++++ drivers/common/cnxk/roc_nix_debug.c | 10 ++++++++-- drivers/common/cnxk/roc_nix_irq.c | 3 +++ drivers/common/cnxk/roc_nix_priv.h | 3 +++ drivers/common/cnxk/roc_nix_queue.c | 14 +++++++++++++- drivers/net/cnxk/cnxk_ethdev.c | 5 +++-- 7 files changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index 425c335bf3..0d8f2a5e9b 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -861,6 +861,7 @@ #define NIX_CQERRINT_DOOR_ERR (0x0ull) #define NIX_CQERRINT_WR_FULL (0x1ull) #define NIX_CQERRINT_CQE_FAULT (0x2ull) +#define NIX_CQERRINT_CPT_DROP (0x3ull) /* [CN10KB, .) */ #define NIX_LINK_SDP (0xdull) /* [CN10K, .) */ #define NIX_LINK_CPT (0xeull) /* [CN10K, .) */ @@ -1009,11 +1010,12 @@ struct nix_cqe_hdr_s { /* NIX completion queue context structure */ struct nix_cq_ctx_s { uint64_t base : 64; /* W0 */ - uint64_t rsvd_67_64 : 4; + uint64_t lbp_ena : 1; + uint64_t lbpid_low : 3; uint64_t bp_ena : 1; - uint64_t rsvd_71_69 : 3; + uint64_t lbpid_med : 3; uint64_t bpid : 9; - uint64_t rsvd_83_81 : 3; + uint64_t lbpid_high : 3; uint64_t qint_idx : 7; uint64_t cq_err : 1; uint64_t cint_idx : 7; @@ -1027,10 +1029,14 @@ struct nix_cq_ctx_s { uint64_t drop : 8; uint64_t drop_ena : 1; uint64_t ena : 1; - uint64_t rsvd_211_210 : 2; - uint64_t substream : 20; + uint64_t cpt_drop_err_en : 1; + uint64_t rsvd_211 : 1; + uint64_t substream : 12; + uint64_t stash_thresh : 4; + uint64_t lbp_frac : 4; uint64_t caching : 1; - uint64_t rsvd_235_233 : 3; + uint64_t stashing : 1; + uint64_t rsvd_235_234 : 2; uint64_t qsize : 4; uint64_t cq_err_int : 8; uint64_t cq_err_int_ena : 8; diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 1985dd771d..848609eb35 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -236,6 +236,12 @@ roc_model_is_cnf10kb_a0(void) return roc_model->flag & ROC_MODEL_CNF105xxN_A0; } +static inline uint64_t +roc_model_is_cn10kb(void) +{ + return roc_model->flag & ROC_MODEL_CN103xx; +} + static inline bool roc_env_is_hw(void) { diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c index 6f82350b53..e491060765 100644 --- a/drivers/common/cnxk/roc_nix_debug.c +++ b/drivers/common/cnxk/roc_nix_debug.c @@ -665,8 +665,14 @@ nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx, FILE *file) ctx->cq_err_int_ena, ctx->cq_err_int); nix_dump(file, "W3: qsize \t\t\t%d\nW3: caching \t\t\t%d", ctx->qsize, ctx->caching); - nix_dump(file, "W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d", ctx->substream, - ctx->ena); + nix_dump(file, "W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d\nW3: lbp_ena \t\t\t%d", + ctx->substream, ctx->ena, ctx->lbp_ena); + nix_dump(file, + "W3: lbpid_high \t\t\t0x%03x\nW3: lbpid_med \t\t\t0x%03x\n" + "W3: lbpid_low \t\t\t0x%03x\n(W3: lbpid) \t\t\t0x%03x", + ctx->lbpid_high, ctx->lbpid_med, ctx->lbpid_low, + ctx->lbpid_high << 6 | ctx->lbpid_med << 3 | ctx->lbpid_low); + nix_dump(file, "W3: lbp_frac \t\t\t%d\n", ctx->lbp_frac); nix_dump(file, "W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d", ctx->drop_ena, ctx->drop); nix_dump(file, "W3: bp \t\t\t\t%d\n", ctx->bp); diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c index 661af79193..2e4bccb713 100644 --- a/drivers/common/cnxk/roc_nix_irq.c +++ b/drivers/common/cnxk/roc_nix_irq.c @@ -287,6 +287,9 @@ nix_lf_q_irq(void *param) if (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) plt_err("CQ=%d NIX_CQERRINT_CQE_FAULT", cq); + + if (irq & BIT_ULL(NIX_CQERRINT_CPT_DROP)) + plt_err("CQ=%d NIX_CQERRINT_CPT_DROP", cq); } /* Handle SQ interrupts */ diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 02290a1b86..0a9461c856 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -16,6 +16,9 @@ /* Apply BP/DROP when CQ is 95% full */ #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100) +#define NIX_CQ_SEC_THRESH_LEVEL (25 * 256 / 100) +/* Apply LBP at 75% of actual BP */ +#define NIX_CQ_LPB_THRESH_FRAC (75 * 16 / 100) #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) #define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 0dd3c8d4df..5fad8e4543 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -743,6 +743,8 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct mbox *mbox = (&nix->dev)->mbox; volatile struct nix_cq_ctx_s *cq_ctx; + uint16_t drop_thresh = NIX_CQ_THRESH_LEVEL; + uint16_t cpt_lbpid = nix->bpid[0]; enum nix_q_size qsize; size_t desc_sz; int rc; @@ -797,6 +799,16 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) cq_ctx->avg_level = 0xff; cq_ctx->cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT); cq_ctx->cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR); + if (roc_model_is_cn10kb() && roc_nix_inl_inb_is_enabled(roc_nix)) { + cq_ctx->cq_err_int_ena |= BIT(NIX_CQERRINT_CPT_DROP); + cq_ctx->cpt_drop_err_en = 1; + cq_ctx->lbp_ena = 1; + cq_ctx->lbpid_low = cpt_lbpid & 0x7; + cq_ctx->lbpid_med = (cpt_lbpid >> 3) & 0x7; + cq_ctx->lbpid_high = (cpt_lbpid >> 6) & 0x7; + cq_ctx->lbp_frac = NIX_CQ_LPB_THRESH_FRAC; + drop_thresh = NIX_CQ_SEC_THRESH_LEVEL; + } /* Many to one reduction */ cq_ctx->qint_idx = cq->qid % nix->qints; @@ -812,7 +824,7 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) cq_ctx->drop_ena = 1; cq->drop_thresh = min_rx_drop; } else { - cq->drop_thresh = NIX_CQ_THRESH_LEVEL; + cq->drop_thresh = drop_thresh; /* Drop processing or red drop cannot be enabled due to * due to packets coming for second pass from CPT. */ diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 1be2e9e776..d711eb6b27 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -49,8 +49,9 @@ nix_inl_cq_sz_clamp_up(struct roc_nix *nix, struct rte_mempool *mp, struct roc_nix_rq *inl_rq; uint64_t limit; + /* For CN10KB and above, LBP needs minimum CQ size */ if (!roc_errata_cpt_hang_on_x2p_bp()) - return nb_desc; + return RTE_MAX(nb_desc, (uint32_t)4096); /* CQ should be able to hold all buffers in first pass RQ's aura * this RQ's aura. @@ -695,7 +696,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, first_skip += RTE_PKTMBUF_HEADROOM; first_skip += rte_pktmbuf_priv_size(lpb_pool); rq->first_skip = first_skip; - rq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mp); + rq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(lpb_pool); rq->lpb_size = lpb_pool->elt_size; if (roc_errata_nix_no_meta_aura()) rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);