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Sun, 8 Jan 2023 23:58:57 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" Subject: [PATCH 6/7] common/mlx5: add LZ4 capabilities check Date: Mon, 9 Jan 2023 09:58:37 +0200 Message-ID: <20230109075838.2508039-7-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230109075838.2508039-1-michaelba@nvidia.com> References: <20230109075838.2508039-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT052:EE_|PH0PR12MB5648:EE_ X-MS-Office365-Filtering-Correlation-Id: d6f7c03f-d7e9-4185-25a2-08daf21764ed X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: e2ZD5qapejRXzZ6V4U9KJ0Q9siQYP/0gjrZtamsJZH7klT3PxqMOzjY3jz4Zru/yNMEgn95LhNI/ovtT7hSjHA2Hkh16np3nssBkgs6K/1yEoLvUWdZcVcqHAWtRbgtmfuUZcK0l9e27S+7lYYIp9vKwhohaul6JTYg2P6o8otHAlUzDzYnhH/C26IUwotorlnDQ4RjzEZOZXDJVw1ttGfD4sReio9GsoBYrxWJ6p8AAzTib9tK+4WrTw/j7NXTJuyRGuxzEc3qrJMINhmvVT3y0Y3gttokXmmj2kHblnioX09U1WvtA5yrV8RnhvbgIhnwRdo6911p+8jpp/aCwr6C2AwY2vtXfE39wz2gwPeRQY0PJBHVJEbQbQdxIt188eP3BnuPGGNzFhzqA2vWDHPmBu6bafEycc8IpXv0EOyHE48XPBa8HQILUQYrrW3hTIn3VtGbTiZF9xNMviI0ErJWfPNTSntex4143UkusiM8Aw/x2KVsls6kqqwKiGGfoNjgxlPe+Ry5jZymr3AxWpCwhPEWbZOiVy5Rdh3W7ANl92/ao6DqYQooYPhQ98vSw2Wh+c7QQ9TxseX3Dhxilc23QtWx13uWQE+gKbbcJD5HTNHNu3ZgViTTclIEIKocDbeVg2A6/xmKr7Svua9Nudy3Z4r+Hs10Iz/4DhChj7RbTlW3imWEYt0zLkgVR+0aTeJCeQ+y0ZpIAlIl+YhRX7Q== X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Signed-off-by: Michael Baum --- drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 8280785e2f..452f37489c 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -998,6 +998,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, log_compress_mmo_size); attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, log_decompress_mmo_size); + attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_data_only); + attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_no_checksum); + attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_checksum); attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, mini_cqe_resp_flow_tag); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index dac86e8a5b..6e92035aaa 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -267,6 +267,9 @@ struct mlx5_hca_attr { uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; uint32_t log_max_mmo_decompress:5; + uint32_t decomp_lz4_data_only_en:1; + uint32_t decomp_lz4_no_checksum_en:1; + uint32_t decomp_lz4_checksum_en:1; uint32_t umr_modify_entity_size_disabled:1; uint32_t umr_indirect_mkey_disabled:1; uint32_t log_min_stride_wqe_sz:5; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index c3a1ce11a4..db7ccdd06d 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -578,9 +578,19 @@ struct mlx5_rdma_write_wqe { #define MLX5_OPC_MOD_MMO_DECOMP 0x3u #define MLX5_OPC_MOD_MMO_DMA 0x1u +#define WQE_GGA_DECOMP_DEFLATE 0x0u +#define WQE_GGA_DECOMP_LZ4 0x2u + +#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u +#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u + #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u +#define WQE_GGA_DECOMP_PARAMS_OFFSET 20u +#define WQE_GGA_DECOMP_TYPE_OFFSET 8u +#define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u + #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u @@ -599,7 +609,7 @@ struct mlx5_gga_wqe { uint32_t opcode; uint32_t sq_ds; uint32_t flags; - uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ + uint32_t gga_ctrl1; uint32_t gga_ctrl2; uint32_t opaque_lkey; uint64_t opaque_vaddr; @@ -1434,7 +1444,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_dma_mmo_size[0x5]; u8 reserved_at_70[0x3]; u8 log_compress_mmo_size[0x5]; - u8 reserved_at_78[0x3]; + u8 decompress_lz4_data_only[0x1]; + u8 decompress_lz4_no_checksum[0x1]; + u8 decompress_lz4_checksum[0x1]; u8 log_decompress_mmo_size[0x5]; u8 log_max_srq_sz[0x8]; u8 log_max_qp_sz[0x8];