[2/2] net/mlx5: add MPLS tunnel support for HWS

Message ID 20230208061911.1644248-3-michaelba@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers
Series net/mlx5: support MPLSoUDP for HWS |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

Michael Baum Feb. 8, 2023, 6:19 a.m. UTC
  Add support for MPLS tunnel item in HWS.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
---
 doc/guides/nics/mlx5.rst               | 4 ++++
 doc/guides/rel_notes/release_23_03.rst | 4 ++++
 drivers/net/mlx5/mlx5_flow_hw.c        | 1 +
 3 files changed, 9 insertions(+)
  

Comments

Slava Ovsiienko March 7, 2023, 12:40 p.m. UTC | #1
> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: среда, 8 февраля 2023 г. 08:19
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Ori Kam
> <orika@nvidia.com>
> Subject: [PATCH 2/2] net/mlx5: add MPLS tunnel support for HWS
> 
> Add support for MPLS tunnel item in HWS.
> 
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
  

Patch

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index f137f156f9..557784844c 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -241,6 +241,10 @@  Limitations
 
 - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.
 
+- MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2).
+
+- MPLSoUDP with multiple MPLS headers is only supported in HW steering (``dv_flow_en`` = 2).
+
 - Match on Geneve header supports the following fields only:
 
      - VNI
diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst
index c15f6fbb9f..2d831d64cb 100644
--- a/doc/guides/rel_notes/release_23_03.rst
+++ b/doc/guides/rel_notes/release_23_03.rst
@@ -55,6 +55,10 @@  New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Updated NVIDIA mlx5 driver.**
+
+  * Added support for MPLSoUDP in hardware steering.
+
 * **Updated Intel QuickAssist Technology (QAT) crypto driver.**
 
   * Added support for SHA3 224/256/384/512 plain hash in QAT GEN 3.
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 20c71ff7f0..828446f45a 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -4725,6 +4725,7 @@  flow_hw_pattern_validate(struct rte_eth_dev *dev,
 		case RTE_FLOW_ITEM_TYPE_GTP:
 		case RTE_FLOW_ITEM_TYPE_GTP_PSC:
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
+		case RTE_FLOW_ITEM_TYPE_MPLS:
 		case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
 		case RTE_FLOW_ITEM_TYPE_GRE:
 		case RTE_FLOW_ITEM_TYPE_GRE_KEY: