[2/2] net/mlx5: add MPLS tunnel support for HWS
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Commit Message
Add support for MPLS tunnel item in HWS.
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
---
doc/guides/nics/mlx5.rst | 4 ++++
doc/guides/rel_notes/release_23_03.rst | 4 ++++
drivers/net/mlx5/mlx5_flow_hw.c | 1 +
3 files changed, 9 insertions(+)
Comments
> -----Original Message-----
> From: Michael Baum <michaelba@nvidia.com>
> Sent: среда, 8 февраля 2023 г. 08:19
> To: dev@dpdk.org
> Cc: Matan Azrad <matan@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Ori Kam
> <orika@nvidia.com>
> Subject: [PATCH 2/2] net/mlx5: add MPLS tunnel support for HWS
>
> Add support for MPLS tunnel item in HWS.
>
> Signed-off-by: Michael Baum <michaelba@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
@@ -241,6 +241,10 @@ Limitations
- L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.
+- MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2).
+
+- MPLSoUDP with multiple MPLS headers is only supported in HW steering (``dv_flow_en`` = 2).
+
- Match on Geneve header supports the following fields only:
- VNI
@@ -55,6 +55,10 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Updated NVIDIA mlx5 driver.**
+
+ * Added support for MPLSoUDP in hardware steering.
+
* **Updated Intel QuickAssist Technology (QAT) crypto driver.**
* Added support for SHA3 224/256/384/512 plain hash in QAT GEN 3.
@@ -4725,6 +4725,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
case RTE_FLOW_ITEM_TYPE_GTP:
case RTE_FLOW_ITEM_TYPE_GTP_PSC:
case RTE_FLOW_ITEM_TYPE_VXLAN:
+ case RTE_FLOW_ITEM_TYPE_MPLS:
case MLX5_RTE_FLOW_ITEM_TYPE_SQ:
case RTE_FLOW_ITEM_TYPE_GRE:
case RTE_FLOW_ITEM_TYPE_GRE_KEY: