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Mon, 20 Feb 2023 23:08:04 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" , Subject: [PATCH v3 2/8] compress/mlx5: fix wrong output Adler-32 checksum offset Date: Tue, 21 Feb 2023 09:07:50 +0200 Message-ID: <20230221070756.3070819-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221070756.3070819-1-michaelba@nvidia.com> References: <20230202162537.1067595-1-michaelba@nvidia.com> <20230221070756.3070819-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT010:EE_|PH0PR12MB7840:EE_ X-MS-Office365-Filtering-Correlation-Id: 4261ccad-2797-4b6b-6f37-08db13da67b9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RnQmktXKHug6FtmkRXa23Xpamff1shApkTUnmzYgsCbMi6WUkUoNWL/EfK15/xS0mgpPIPoDzQnbi4UwlTjcYtBzPYLSYGd9ns0cJ0R2mY7Y9b6ieqNYWG1qlvNssovq/vzjbGaYb1qbKeK3eY739lp/og3Sz1E+gMe2rA+cPyDJY/JjJyi4arAZf30VXrK0saXhiQAIo1nZiVPkkGyU52wFlkqHOFGcCh68jxfvOsn1asD51rldRPI+FT0ba3LFtLhdDicjpvOBaAr5HfcXXYVMxXrykj0EKZZMRF0/+2V3kEOMQ6vbSiB2L+uZB6Zkc5WwKnWbWTZRxx0hVo6oJRFB+gD6iDlHmsCJQKlMaeZvLAfHm/tvOe42f74F/exWciWT3MNLPrwhgH/Vw3kEGZFHkzLuU21x8XCWfyHzNhuRHpl7XEONMBFSikZM22kNrq6ttCMsdxZBsQnkuK9tJrJgCWZrUB0QAH/OzmgJu90tAncOzDadVDmxWvdJi13uSE+MhraL47PF/ynq+G5sOUbMd5SphXPwdSvFqh1xQGdFOC2cB3DV5QPxSSytT4Ak1TuBmivvC6bfGt9fq2FtGFq9hj4Wvkabjqh2Usl47kRwhjPTVJfrTyBnwtU5tf+fAaS1WcR4orawdGEv9wR3HQsPS3mar0P+mi90CydXRBb4WR7FVB62loTwjfjBKyxA7nz5A8Q0seqo73U/OVyPzA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199018)(36840700001)(40470700004)(46966006)(36756003)(5660300002)(36860700001)(8936002)(83380400001)(47076005)(426003)(40460700003)(86362001)(40480700001)(7696005)(55016003)(7636003)(70586007)(54906003)(336012)(478600001)(82310400005)(316002)(6916009)(41300700001)(4326008)(8676002)(356005)(2616005)(6286002)(1076003)(6666004)(70206006)(26005)(186003)(82740400003)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2023 07:08:16.5030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4261ccad-2797-4b6b-6f37-08db13da67b9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7840 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org After de/compress dequeue, the output checksum is copied into the op structure. The "output_checksum" field in op structure is "uint64_t" type, and the 32-bit checksums (CRC32, Adler-32) are copied into the lower 32 bits. When both CRC32 and Adler-32 are configured, CRC32 is copied into the lower 32 bits and Adler-32 into the upper 32 bits. However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the upper 32 bits. This patch updates Adler-32 output checksun to be copied into the lower 32 bits. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Cc: matan@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 06d1ff5b95..82088a7b8c 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, break; case RTE_COMP_CHECKSUM_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 - (opaq[idx].adler32) << 32; + (opaq[idx].adler32); break; case RTE_COMP_CHECKSUM_CRC32_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32