diff mbox series

[v2,05/11] crypto/cnxk: set ctx for AE

Message ID	20230224094014.3246764-6-ktejasree@marvell.com (mailing list archive)
State	Accepted, archived
Delegated to:	akhil goyal
Headers	From: Tejasree Kondoj <ktejasree@marvell.com> To: Akhil Goyal <gakhil@marvell.com> CC: Anoob Joseph <anoobj@marvell.com>, Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>, <dev@dpdk.org> Subject: [PATCH v2 05/11] crypto/cnxk: set ctx for AE Date: Fri, 24 Feb 2023 15:10:08 +0530 Message-ID: <20230224094014.3246764-6-ktejasree@marvell.com> In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	fixes and improvements to cnxk crypto PMD \| [v2,00/11] fixes and improvements to cnxk crypto PMD [v2,01/11] common/cnxk: fix incorrect auth key length [v2,02/11] crypto/cnxk: make sg version check const [v2,03/11] crypto/cnxk: use version field directly [v2,04/11] crypto/cnxk: use direct mode for zero aad length [v2,05/11] crypto/cnxk: set ctx for AE [v2,06/11] common/cnxk: ensure flush inval completion with CSR read [v2,07/11] common/cnxk: add errata function for CPT set ctx [v2,08/11] common/cnxk: replace CPT revision check with caps [v2,09/11] crypto/cnxk: support cn10k IPsec SG mode [v2,10/11] crypto/cnxk: fix order of ECFPM params [v2,11/11] crypto/cnxk: add model check for pdcp chain

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Tejasree Kondoj Feb. 24, 2023, 9:40 a.m. UTC

  Set ctx_val to 1 for asymmetric ops.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 18 ++++---------
 drivers/crypto/cnxk/cn9k_cryptodev_ops.c  | 16 +++--------
 drivers/crypto/cnxk/cnxk_ae.h             | 21 +++++++++++++++
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c  | 33 ++++++++++++++++-------
 4 files changed, 53 insertions(+), 35 deletions(-)

Comments

Akhil Goyal Feb. 27, 2023, 5:38 p.m. UTC | #1

> Subject: [PATCH v2 05/11] crypto/cnxk: set ctx for AE
> 
> Set ctx_val to 1 for asymmetric ops.
> 

Please justify patch with proper description.

> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>

Tejasree Kondoj Feb. 28, 2023, 5:40 a.m. UTC | #2

Hi Akhil,

Patch sets ctx_val to 1 for asymmetric due to cn10k A0 hardware errata and structures are redesigned to satisfy hardware alignment requirements.

Thanks
Tejasree

> -----Original Message-----
> From: Akhil Goyal <gakhil@marvell.com>
> Sent: Monday, February 27, 2023 11:09 PM
> To: Tejasree Kondoj <ktejasree@marvell.com>
> Cc: Anoob Joseph <anoobj@marvell.com>; Gowrishankar Muthukrishnan
> <gmuthukrishn@marvell.com>; dev@dpdk.org
> Subject: RE: [PATCH v2 05/11] crypto/cnxk: set ctx for AE
> 
> > Subject: [PATCH v2 05/11] crypto/cnxk: set ctx for AE
> >
> > Set ctx_val to 1 for asymmetric ops.
> >
> 
> Please justify patch with proper description.
> 
> > Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>

diff mbox series

Patch

diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
index 92f7002db9..d1a43eaf13 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
@@ -158,10 +158,8 @@  cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct
 
 		if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
 			asym_op = op->asym;
-			ae_sess = (struct cnxk_ae_sess *)
-					asym_op->session->sess_private_data;
-			ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0],
-					      ae_sess);
+			ae_sess = (struct cnxk_ae_sess *)asym_op->session;
+			ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0], ae_sess);
 			if (unlikely(ret))
 				return 0;
 			w7 = ae_sess->cpt_inst_w7;
@@ -330,10 +328,9 @@  cn10k_cpt_crypto_adapter_ev_mdata_set(struct rte_cryptodev *dev __rte_unused, vo
 			return -EINVAL;
 	} else if (op_type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
 		if (sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
-			struct rte_cryptodev_asym_session *asym_sess = sess;
 			struct cnxk_ae_sess *priv;
 
-			priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data;
+			priv = (struct cnxk_ae_sess *)sess;
 			priv->qp = qp;
 			priv->cpt_inst_w2 = w2;
 		} else
@@ -381,11 +378,9 @@  cn10k_ca_meta_info_extract(struct rte_crypto_op *op, struct cnxk_cpt_qp **qp, ui
 		}
 	} else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
 		if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
-			struct rte_cryptodev_asym_session *asym_sess;
 			struct cnxk_ae_sess *priv;
 
-			asym_sess = op->asym->session;
-			priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data;
+			priv = (struct cnxk_ae_sess *)op->asym->session;
 			*qp = priv->qp;
 			*w2 = priv->cpt_inst_w2;
 		} else
@@ -890,10 +885,7 @@  cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,
 		} else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
 			struct rte_crypto_asym_op *op = cop->asym;
 			uintptr_t *mdata = infl_req->mdata;
-			struct cnxk_ae_sess *sess;
-
-			sess = (struct cnxk_ae_sess *)
-					op->session->sess_private_data;
+			struct cnxk_ae_sess *sess = (struct cnxk_ae_sess *)op->session;
 
 			cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]);
 		}
diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
index 11541b6ab9..34d40b07d4 100644
--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c
@@ -105,13 +105,10 @@  cn9k_cpt_inst_prep(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,
 			inst->w7.u64 = sess->cpt_inst_w7;
 		}
 	} else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
-		struct rte_crypto_asym_op *asym_op;
 		struct cnxk_ae_sess *sess;
 
 		if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
-			asym_op = op->asym;
-			sess = (struct cnxk_ae_sess *)
-					asym_op->session->sess_private_data;
+			sess = (struct cnxk_ae_sess *)op->asym->session;
 			ret = cnxk_ae_enqueue(qp, op, infl_req, inst, sess);
 			inst->w7.u64 = sess->cpt_inst_w7;
 		} else {
@@ -345,7 +342,7 @@  cn9k_cpt_crypto_adapter_ev_mdata_set(struct rte_cryptodev *dev __rte_unused,
 			struct rte_cryptodev_asym_session *asym_sess = sess;
 			struct cnxk_ae_sess *priv;
 
-			priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data;
+			priv = (struct cnxk_ae_sess *)asym_sess;
 			priv->qp = qp;
 			priv->cpt_inst_w2 = w2;
 		} else
@@ -393,11 +390,9 @@  cn9k_ca_meta_info_extract(struct rte_crypto_op *op,
 		}
 	} else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
 		if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
-			struct rte_cryptodev_asym_session *asym_sess;
 			struct cnxk_ae_sess *priv;
 
-			asym_sess = op->asym->session;
-			priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data;
+			priv = (struct cnxk_ae_sess *)op->asym->session;
 			*qp = priv->qp;
 			inst->w2.u64 = priv->cpt_inst_w2;
 		} else
@@ -609,10 +604,7 @@  cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop,
 		} else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
 			struct rte_crypto_asym_op *op = cop->asym;
 			uintptr_t *mdata = infl_req->mdata;
-			struct cnxk_ae_sess *sess;
-
-			sess = (struct cnxk_ae_sess *)
-					op->session->sess_private_data;
+			struct cnxk_ae_sess *sess = (struct cnxk_ae_sess *)op->session;
 
 			cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]);
 		}
diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h
index 698c10129e..b7c13a9e01 100644
--- a/drivers/crypto/cnxk/cnxk_ae.h
+++ b/drivers/crypto/cnxk/cnxk_ae.h
@@ -13,7 +13,10 @@ 
 
 #include "cnxk_cryptodev_ops.h"
 
+#define ASYM_SESS_SIZE sizeof(struct rte_cryptodev_asym_session)
+
 struct cnxk_ae_sess {
+	uint8_t rte_sess[ASYM_SESS_SIZE];
 	enum rte_crypto_asym_xform_type xfrm_type;
 	union {
 		struct rte_crypto_rsa_xform rsa_ctx;
@@ -25,6 +28,24 @@  struct cnxk_ae_sess {
 	uint64_t cpt_inst_w7;
 	uint64_t cpt_inst_w2;
 	struct cnxk_cpt_qp *qp;
+	struct roc_cpt_lf *lf;
+	struct hw_ctx_s {
+		union {
+			struct {
+				uint64_t rsvd : 48;
+
+				uint64_t ctx_push_size : 7;
+				uint64_t rsvd1 : 1;
+
+				uint64_t ctx_hdr_size : 2;
+				uint64_t aop_valid : 1;
+				uint64_t rsvd2 : 1;
+				uint64_t ctx_size : 4;
+			} s;
+			uint64_t u64;
+		} w0;
+		uint8_t rsvd[256];
+	} hw_ctx __plt_aligned(ROC_ALIGN);
 };
 
 static __rte_always_inline void
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 27f2846f74..f03646fe1a 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -760,14 +760,14 @@  cnxk_ae_session_size_get(struct rte_cryptodev *dev __rte_unused)
 }
 
 void
-cnxk_ae_session_clear(struct rte_cryptodev *dev,
-		      struct rte_cryptodev_asym_session *sess)
+cnxk_ae_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_asym_session *sess)
 {
-	struct cnxk_ae_sess *priv;
+	struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess;
 
-	priv = (struct cnxk_ae_sess *) sess->sess_private_data;
-	if (priv == NULL)
-		return;
+	/* Trigger CTX flush + invalidate to remove from CTX_CACHE */
+	roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true);
+
+	plt_delay_ms(1);
 
 	/* Free resources allocated in session_cfg */
 	cnxk_ae_free_session_parameters(priv);
@@ -777,23 +777,36 @@  cnxk_ae_session_clear(struct rte_cryptodev *dev,
 }
 
 int
-cnxk_ae_session_cfg(struct rte_cryptodev *dev,
-		    struct rte_crypto_asym_xform *xform,
+cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xform,
 		    struct rte_cryptodev_asym_session *sess)
 {
-	struct cnxk_ae_sess *priv =
-			(struct cnxk_ae_sess *) sess->sess_private_data;
+	struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess;
 	struct cnxk_cpt_vf *vf = dev->data->dev_private;
 	struct roc_cpt *roc_cpt = &vf->cpt;
 	union cpt_inst_w7 w7;
+	struct hw_ctx_s *hwc;
 	int ret;
 
 	ret = cnxk_ae_fill_session_parameters(priv, xform);
 	if (ret)
 		return ret;
 
+	priv->lf = roc_cpt->lf[0];
+
 	w7.u64 = 0;
 	w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE];
+
+	if (vf->cpt.cpt_revision == ROC_CPT_REVISION_ID_106XX) {
+		hwc = &priv->hw_ctx;
+		hwc->w0.s.aop_valid = 1;
+		hwc->w0.s.ctx_hdr_size = 0;
+		hwc->w0.s.ctx_size = 1;
+		hwc->w0.s.ctx_push_size = 1;
+
+		w7.s.cptr = (uint64_t)hwc;
+		w7.s.ctx_val = 1;
+	}
+
 	priv->cpt_inst_w7 = w7.u64;
 	priv->cnxk_fpm_iova = vf->cnxk_fpm_iova;
 	priv->ec_grp = vf->ec_grp;