Extend rxq_cqe_comp_en devarg to allow the Enhanced CQE Compression
layout to be enabled by a user. Setting the 8th bit turns it on.
For example, rxq_cqe_comp_en=0x84 means the L3/L4 Header miniCQE format
and the Enhanced CQE Compression layout.
Enhanced CQE Compression can be enabled only if it is supported by FW.
Create CQ with the proper CQE compression layout based on capabilities.
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
doc/guides/nics/mlx5.rst | 14 ++++++++++----
doc/guides/rel_notes/release_23_03.rst | 1 +
drivers/net/mlx5/mlx5.c | 17 ++++++++++++++---
drivers/net/mlx5/mlx5.h | 1 +
drivers/net/mlx5/mlx5_devx.c | 2 ++
5 files changed, 28 insertions(+), 7 deletions(-)
@@ -681,14 +681,20 @@ for an additional list of options shared with other mlx5 drivers.
Multi-Packet Rx queue configuration: Hash RSS format is used in case
MPRQ is disabled, Checksum format is used in case MPRQ is enabled.
- Specifying 2 as a ``rxq_cqe_comp_en`` value selects Flow Tag format for
- better compression rate in case of RTE Flow Mark traffic.
- Specifying 3 as a ``rxq_cqe_comp_en`` value selects Checksum format.
- Specifying 4 as a ``rxq_cqe_comp_en`` value selects L3/L4 Header format for
+ The lower 3 bits define the CQE compression format:
+ Specifying 2 in these bits of the ``rxq_cqe_comp_en`` parameter selects
+ Flow Tag format for better compression rate in case of RTE Flow Mark traffic.
+ Specifying 3 in these bits selects Checksum format.
+ Specifying 4 in these bits selects L3/L4 Header format for
better compression rate in case of mixed TCP/UDP and IPv4/IPv6 traffic.
CQE compression format selection requires DevX to be enabled. If there is
no DevX enabled/supported the value is reset to 1 by default.
+ 8th bit defines the CQE compression layout.
+ Setting this bit to 1 turns Enhanced CQE Compression Layout on.
+ Enhanced CQE Compression is designed for better latency and SW utilization.
+ This bit is ignored if the Basic CQE compression layout is only supported.
+
Supported on:
- x86_64 with ConnectX-4, ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,
@@ -155,6 +155,7 @@ New Features
* **Updated NVIDIA mlx5 driver.**
* Added support for matching on ICMPv6 ID and sequence fields.
+ * Added support for Enhanced CQE Compression layout.
* **Updated Wangxun ngbe driver.**
@@ -384,6 +384,8 @@ static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
#define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
+#define MLX5_RXQ_ENH_CQE_COMP_MASK 0x80
+
/**
* Decide whether representor ID is a HPF(host PF) port on BF2.
*
@@ -2461,14 +2463,16 @@ mlx5_port_args_check_handler(const char *key, const char *val, void *opaque)
return -rte_errno;
}
if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
- if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
+ if ((tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK) >
+ MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
DRV_LOG(ERR, "invalid CQE compression "
"format parameter");
rte_errno = EINVAL;
return -rte_errno;
}
config->cqe_comp = !!tmp;
- config->cqe_comp_fmt = tmp;
+ config->cqe_comp_fmt = tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK;
+ config->enh_cqe_comp = !!(tmp & MLX5_RXQ_ENH_CQE_COMP_MASK);
} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
config->hw_padding = !!tmp;
} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
@@ -2640,7 +2644,13 @@ mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist,
"L3/L4 Header CQE compression format isn't supported.");
config->cqe_comp = 0;
}
- DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.",
+ if (config->enh_cqe_comp && !hca_attr->enhanced_cqe_compression) {
+ DRV_LOG(WARNING,
+ "Enhanced CQE compression isn't supported.");
+ config->enh_cqe_comp = 0;
+ }
+ DRV_LOG(DEBUG, "%sRx CQE compression is %ssupported.",
+ config->enh_cqe_comp ? "Enhanced " : "",
config->cqe_comp ? "" : "not ");
if ((config->std_delay_drop || config->hp_delay_drop) &&
!dev_cap->rq_delay_drop_en) {
@@ -2662,6 +2672,7 @@ mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist,
DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding);
DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp);
DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt);
+ DRV_LOG(DEBUG, "\"enh_cqe_comp\" is %u.", config->enh_cqe_comp);
DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en);
DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.",
config->std_delay_drop);
@@ -271,6 +271,7 @@ struct mlx5_port_config {
unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
unsigned int hw_padding:1; /* End alignment padding is supported. */
unsigned int cqe_comp:1; /* CQE compression is enabled. */
+ unsigned int enh_cqe_comp:1; /* Enhanced CQE compression is enabled. */
unsigned int cqe_comp_fmt:3; /* CQE compression format. */
unsigned int rx_vec_en:1; /* Rx vector is enabled. */
unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */
@@ -372,6 +372,8 @@ mlx5_rxq_create_devx_cq_resources(struct mlx5_rxq_priv *rxq)
if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
!rxq_data->lro) {
cq_attr.cqe_comp_en = 1u;
+ cq_attr.cqe_comp_layout = priv->config.enh_cqe_comp;
+ rxq_data->cqe_comp_layout = cq_attr.cqe_comp_layout;
rxq_data->mcqe_format = priv->config.cqe_comp_fmt;
rxq_data->byte_mask = UINT32_MAX;
switch (priv->config.cqe_comp_fmt) {