diff mbox series

crypto/qat: fix SM3 auth mode

Message ID 20230301135915.2184760-1-ciara.power@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series crypto/qat: fix SM3 auth mode |

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ci/loongarch-unit-testing success Unit Testing PASS
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ci/iol-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS

Commit Message

Power, Ciara March 1, 2023, 1:59 p.m. UTC 
  The SM3 auth mode is now set to 0 for QAT, to support plain hash only.
This should also be added to the capabilities for GEN3 and GEN4.
SM3 HMAC is not supported.

Fixes: 75fd4bbc94ab ("crypto/qat: support SM3 hash algorithm")
Cc: arkadiuszx.kusztal@intel.com
Cc: stable@dpdk.org

Signed-off-by: Ciara Power <ciara.power@intel.com>
---
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 3 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 3 +++
 drivers/crypto/qat/qat_sym_session.c         | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

Comments

Arkadiusz Kusztal March 1, 2023, 7:17 p.m. UTC | #1 
> -----Original Message-----
> From: Power, Ciara <ciara.power@intel.com>
> Sent: Wednesday, March 1, 2023 2:59 PM
> To: Ji, Kai <kai.ji@intel.com>
> Cc: dev@dpdk.org; Power, Ciara <ciara.power@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>; stable@dpdk.org
> Subject: [PATCH] crypto/qat: fix SM3 auth mode
> 
> The SM3 auth mode is now set to 0 for QAT, to support plain hash only.
> This should also be added to the capabilities for GEN3 and GEN4.
> SM3 HMAC is not supported.
> 
> Fixes: 75fd4bbc94ab ("crypto/qat: support SM3 hash algorithm")
> Cc: arkadiuszx.kusztal@intel.com
> Cc: stable@dpdk.org
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>
> ---
>  drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 3 +++
> drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 3 +++
>  drivers/crypto/qat/qat_sym_session.c         | 2 +-
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/crypto/qat/qat_sym_session.c
> b/drivers/crypto/qat/qat_sym_session.c
> index 466482d225..6ad6c7ee3a 100644
> --- a/drivers/crypto/qat/qat_sym_session.c
> +++ b/drivers/crypto/qat/qat_sym_session.c
> @@ -697,7 +697,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev
> *dev,
>  	switch (auth_xform->algo) {
>  	case RTE_CRYPTO_AUTH_SM3:
>  		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;
> -		session->auth_mode = ICP_QAT_HW_AUTH_MODE2;
> +		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
>  		break;
>  	case RTE_CRYPTO_AUTH_SHA1:
>  		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
> --
> 2.25.1

Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Akhil Goyal March 11, 2023, 6:54 p.m. UTC | #2 
> > Subject: [PATCH] crypto/qat: fix SM3 auth mode
> >
> > The SM3 auth mode is now set to 0 for QAT, to support plain hash only.
> > This should also be added to the capabilities for GEN3 and GEN4.
> > SM3 HMAC is not supported.
> >
> > Fixes: 75fd4bbc94ab ("crypto/qat: support SM3 hash algorithm")
> > Cc: arkadiuszx.kusztal@intel.com
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Ciara Power <ciara.power@intel.com>
> Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Applied to dpdk-next-crypto

Thanks.
diff mbox series

Patch

diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index 5fa898dc8f..6013fed721 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -152,6 +152,9 @@  static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = {
 	QAT_SYM_CIPHER_CAP(SM4_CTR,
 		CAP_SET(block_size, 16),
 		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
+	QAT_SYM_PLAIN_AUTH_CAP(SM3,
+		CAP_SET(block_size, 64),
+		CAP_RNG(digest_size, 32, 32, 0)),
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
index b1e5fa9a82..b219a418ba 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
@@ -100,6 +100,9 @@  static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = {
 	QAT_SYM_CIPHER_CAP(SM4_CTR,
 		CAP_SET(block_size, 16),
 		CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
+	QAT_SYM_PLAIN_AUTH_CAP(SM3,
+		CAP_SET(block_size, 64),
+		CAP_RNG(digest_size, 32, 32, 0)),
 	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 466482d225..6ad6c7ee3a 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -697,7 +697,7 @@  qat_sym_session_configure_auth(struct rte_cryptodev *dev,
 	switch (auth_xform->algo) {
 	case RTE_CRYPTO_AUTH_SM3:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;
-		session->auth_mode = ICP_QAT_HW_AUTH_MODE2;
+		session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
 		break;
 	case RTE_CRYPTO_AUTH_SHA1:
 		session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;