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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT114.mail.protection.outlook.com (10.13.172.206) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.31 via Frontend Transport; Wed, 12 Apr 2023 17:07:48 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 12 Apr 2023 10:07:39 -0700 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 12 Apr 2023 10:07:37 -0700 From: Viacheslav Ovsiienko To: CC: , , Subject: [PATCH v2] common/mlx5: enable operation in iova virtual address mode Date: Wed, 12 Apr 2023 20:07:23 +0300 Message-ID: <20230412170723.20722-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230412125320.8585-1-viacheslavo@nvidia.com> References: <20230412125320.8585-1-viacheslavo@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT114:EE_|SN7PR12MB7955:EE_ X-MS-Office365-Filtering-Correlation-Id: e1b3bb32-d8a2-4114-03e4-08db3b78712a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230028)(4636009)(376002)(396003)(346002)(39860400002)(136003)(451199021)(36840700001)(40470700004)(46966006)(40460700003)(966005)(70586007)(7696005)(54906003)(478600001)(8676002)(6916009)(4326008)(70206006)(316002)(41300700001)(36756003)(86362001)(83380400001)(336012)(426003)(26005)(2616005)(1076003)(107886003)(47076005)(6666004)(2906002)(5660300002)(55016003)(40480700001)(8936002)(186003)(16526019)(6286002)(82740400003)(356005)(34070700002)(7636003)(36860700001)(82310400005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Apr 2023 17:07:48.2187 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1b3bb32-d8a2-4114-03e4-08db3b78712a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7955 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The ConnectX NIC series hardware provides advanced internal MMU option and can operate directly over virtual addresses, the host software should not care about any virtual-to-physical address translations. It means the mlx5 PMDs can operate in DPDK IOVA VA (virtual address) mode transparently. To force IOVA VA mode the DPDK should be built with meson option: enable_iova_as_pa=false With this option only drivers supporting IOVA VA mode are enabled. This patch marks mlx5 drivers with require_iova_in_mbuf flag false value, thus allowing their compilation for IOVA VA mode. Signed-off-by: Viacheslav Ovsiienko Acked-by: Morten Brørup --- v1: http://patches.dpdk.org/project/dpdk/patch/20230412125320.8585-1-viacheslavo@nvidia.com/ v2: fixed typos in commit message, reworded a little bit --- drivers/common/mlx5/meson.build | 2 ++ drivers/compress/mlx5/meson.build | 2 ++ drivers/crypto/mlx5/meson.build | 2 ++ drivers/net/mlx5/meson.build | 2 ++ drivers/regex/mlx5/meson.build | 2 ++ 5 files changed, 10 insertions(+) diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build index 9dc809f192..26c6d80fe1 100644 --- a/drivers/common/mlx5/meson.build +++ b/drivers/common/mlx5/meson.build @@ -42,6 +42,8 @@ else cflags += [ '-UPEDANTIC' ] endif +require_iova_in_mbuf = false + mlx5_config = configuration_data() subdir(exec_env) configure_file(output: 'mlx5_autoconf.h', configuration: mlx5_config) diff --git a/drivers/compress/mlx5/meson.build b/drivers/compress/mlx5/meson.build index c906f2d7a2..26a0e0cd09 100644 --- a/drivers/compress/mlx5/meson.build +++ b/drivers/compress/mlx5/meson.build @@ -28,3 +28,5 @@ foreach option:cflags_options cflags += option endif endforeach + +require_iova_in_mbuf = false diff --git a/drivers/crypto/mlx5/meson.build b/drivers/crypto/mlx5/meson.build index a830a4c7b9..a2691ec0f0 100644 --- a/drivers/crypto/mlx5/meson.build +++ b/drivers/crypto/mlx5/meson.build @@ -30,3 +30,5 @@ foreach option:cflags_options cflags += option endif endforeach + +require_iova_in_mbuf = false diff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build index dba911693e..fde7241f7e 100644 --- a/drivers/net/mlx5/meson.build +++ b/drivers/net/mlx5/meson.build @@ -77,6 +77,8 @@ else cflags += [ '-UPEDANTIC' ] endif +require_iova_in_mbuf = false + testpmd_sources += files('mlx5_testpmd.c') subdir(exec_env) diff --git a/drivers/regex/mlx5/meson.build b/drivers/regex/mlx5/meson.build index 87404101b9..0f4ca46f44 100644 --- a/drivers/regex/mlx5/meson.build +++ b/drivers/regex/mlx5/meson.build @@ -32,3 +32,5 @@ foreach option:cflags_options cflags += option endif endforeach + +require_iova_in_mbuf = false