From patchwork Tue Apr 18 08:25:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sivaprasad Tummala X-Patchwork-Id: 126224 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4A04B4297B; Tue, 18 Apr 2023 10:26:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34F2042D29; Tue, 18 Apr 2023 10:26:04 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2064.outbound.protection.outlook.com [40.107.223.64]) by mails.dpdk.org (Postfix) with ESMTP id 8697A40698 for ; Tue, 18 Apr 2023 10:25:59 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f29r/oLAVZDZFoE0oyXhvtJzx1NlFTTS0T6b/Hu49TbqjmMk7bHBbk8BHufTlthkqpq9RLEV1TF5QuV90XqjZla0efbxHHnaZKRYy4p8yZ55JftTceMopO7cgOJtO2lYy+u2Hu9EXBL5zRVa8qsSWo4g81GsH5JuGRcUvHF7NoXbeObjtCmdW/bznhg2SeRnXvgLRC9bVulm7Yh6WYY3SxlsCq1IvMtzdVuP1YkoStsmnnD/t6tIcOKUJSEzBQrHLidwXNgnUhZUT1KPdyvKZligiilWgrzSgzXOQKfPjgsJbNGkVDZh55SFUH6twjrfmJxijtez3HCvN1wL3osxyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kDmlMEPAOfSVV+j5JFKTzeZYLPqp+u/Cq9uu0cThPGo=; b=GrbAe4XzeS6qQSc+yw8aLoyzrUucB4iF00P82kCLRjOn7DDajG+79DLqOTIWRl7uLMl2w61qq/KWo97WgOo0aG/weMXXae56qEzolG4+WKoM595ijthkER1U8Cj9AIzZVZUavVVhTb8G2YTm41zqjRqXj3wGPORQJWXr/R9mMndvWsB7km9eQBTYnWARTXD/yZTf4lAEkqAZWwW0r+6VtHycxQFOYqwyyG35yZ9dfTSXbyQyE74YbVYxkFrgz0tTdQ095InwbxPoFRT0r284pjbBGPtlFIHzWIlPF4J46BHcQXAxrX/8u+JHoqdLwL1HkmpHe5Zd/obyWhF0KPXqyA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kDmlMEPAOfSVV+j5JFKTzeZYLPqp+u/Cq9uu0cThPGo=; b=YzSDD0b27nYE2qid62/aMMCL2cNso4nEM3UdUMZi+OgRv37dIGBkJm3VZ/yVau3JqC+vIY3wTNByWTGLkK/XJ46QyntMRLfGXmbMdJ0+WSOWMzI/73A2diw8/XdIFomxmXmJaqF7dVWYXY3dkHcrfK56hELFNljRLu5oHwU13Xk= Received: from BN9PR03CA0283.namprd03.prod.outlook.com (2603:10b6:408:f5::18) by DM6PR12MB4402.namprd12.prod.outlook.com (2603:10b6:5:2a5::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.45; Tue, 18 Apr 2023 08:25:57 +0000 Received: from BN8NAM11FT053.eop-nam11.prod.protection.outlook.com (2603:10b6:408:f5:cafe::f8) by BN9PR03CA0283.outlook.office365.com (2603:10b6:408:f5::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.46 via Frontend Transport; Tue, 18 Apr 2023 08:25:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT053.mail.protection.outlook.com (10.13.177.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6319.20 via Frontend Transport; Tue, 18 Apr 2023 08:25:57 +0000 Received: from telco-siena.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 18 Apr 2023 03:25:53 -0500 From: Sivaprasad Tummala To: CC: , , Subject: [PATCH v4 4/4] power: amd power monitor support Date: Tue, 18 Apr 2023 01:25:29 -0700 Message-ID: <20230418082529.544777-5-sivaprasad.tummala@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230418082529.544777-1-sivaprasad.tummala@amd.com> References: <20230417043136.470110-1-sivaprasad.tummala@amd.com> <20230418082529.544777-1-sivaprasad.tummala@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT053:EE_|DM6PR12MB4402:EE_ X-MS-Office365-Filtering-Correlation-Id: c6d67b32-ca02-439c-1ee7-08db3fe688ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YT1R/ujInrFGSNkcH3T88I8BtSs1POL02phF8GmEVxCMaSo2v1UR7asKVWY0XFVBgYi3AYAwGHp4nWk3oJQlxJpcqE6N5cmmaCYZEasCeIl0JqcVSoUDyE4aZiV9u18JdaXKff11K1/YHISlPNqiJUZvSLMkYJztGcCE5UwuK+f+Biff41QrQ0JOAQ7sKD+LjL/Ady+Prgk3jVnyE+4ImXsLF+wHBtKU7z7Gj4agpT3sAPMtMDYgvi7+tbsi+NO+JagZQCDOKC/I9bUKCPwOkP5mYtBOAfUICg+Arsn6Zr9dqwgkzx4ZhGdC8ZJCw8Qo5sv9r5ZXvDLL/uzauLXPVY9roQUlZLulB17/W5Gyaxfcb94pL0r6/XPU7eLFowD5m9ZRWpbaJRmXUsfUxoQ8d6WZGF2yiGWUZEjs0cl4MX1Rv+tSk2I82lm5WU+X4+dOlzD+yZW05eAkOHqu0UXSJ4XMNWvzH3OVWvYDU9Atc9akpHsC25OwUmJ0likeb9Yza5UkUI7YAtWwrRj34IZ+bfjxx8KKab5YzuxjDW3sNWQqY4fO/c06mnckdJvLnra2gulJOkEbmPWZKO43BsFz8bGnulGgnyygMcHo5+O568wvF6KNq4iSbfihG6jSdUnVyKi5VZwbSOco2eZnnucva6jp+ynqnKy1nClsehuiJWZuPAhJPVPLxeOn5ksIhx7uuyA9ACI1K1YR8/6Lqh72Wnw65sC49QN8UZKU05EJzFE= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199021)(36840700001)(40470700004)(46966006)(36756003)(8936002)(8676002)(40460700003)(44832011)(5660300002)(2906002)(82310400005)(86362001)(40480700001)(478600001)(7696005)(6666004)(54906003)(16526019)(186003)(2616005)(36860700001)(1076003)(70586007)(70206006)(26005)(41300700001)(356005)(82740400003)(316002)(83380400001)(81166007)(6916009)(4326008)(47076005)(426003)(336012)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2023 08:25:57.1515 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6d67b32-ca02-439c-1ee7-08db3fe688ba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4402 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org mwaitx allows EPYC processors to enter a implementation dependent power/performance optimized state (C1 state) for a specific period or until a store to the monitored address range. Signed-off-by: Sivaprasad Tummala Acked-by: Anatoly Burakov --- lib/eal/x86/rte_power_intrinsics.c | 77 +++++++++++++++++++++++++----- 1 file changed, 66 insertions(+), 11 deletions(-) diff --git a/lib/eal/x86/rte_power_intrinsics.c b/lib/eal/x86/rte_power_intrinsics.c index 6eb9e50807..27055bab52 100644 --- a/lib/eal/x86/rte_power_intrinsics.c +++ b/lib/eal/x86/rte_power_intrinsics.c @@ -17,6 +17,60 @@ static struct power_wait_status { volatile void *monitor_addr; /**< NULL if not currently sleeping */ } __rte_cache_aligned wait_status[RTE_MAX_LCORE]; +/** + * These functions uses UMONITOR/UMWAIT instructions and will enter C0.2 state. + * For more information about usage of these instructions, please refer to + * Intel(R) 64 and IA-32 Architectures Software Developer's Manual. + */ +static void intel_umonitor(volatile void *addr) +{ + /* UMONITOR */ + asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7;" + : + : "D"(addr)); +} + +static void intel_umwait(const uint64_t timeout) +{ + const uint32_t tsc_l = (uint32_t)timeout; + const uint32_t tsc_h = (uint32_t)(timeout >> 32); + /* UMWAIT */ + asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7;" + : /* ignore rflags */ + : "D"(0), /* enter C0.2 */ + "a"(tsc_l), "d"(tsc_h)); +} + +/** + * These functions uses MONITORX/MWAITX instructions and will enter C1 state. + * For more information about usage of these instructions, please refer to + * AMD64 Architecture Programmer’s Manual. + */ +static void amd_monitorx(volatile void *addr) +{ + /* MONITORX */ + asm volatile(".byte 0x0f, 0x01, 0xfa;" + : + : "a"(addr), + "c"(0), /* no extensions */ + "d"(0)); /* no hints */ +} + +static void amd_mwaitx(const uint64_t timeout) +{ + /* MWAITX */ + asm volatile(".byte 0x0f, 0x01, 0xfb;" + : /* ignore rflags */ + : "a"(0), /* enter C1 */ + "c"(2), /* enable timer */ + "b"(timeout)); +} + +static struct { + void (*mmonitor)(volatile void *addr); + void (*mwait)(const uint64_t timeout); +} __rte_cache_aligned power_monitor_ops; + static inline void __umwait_wakeup(volatile void *addr) { @@ -75,8 +129,6 @@ int rte_power_monitor(const struct rte_power_monitor_cond *pmc, const uint64_t tsc_timestamp) { - const uint32_t tsc_l = (uint32_t)tsc_timestamp; - const uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32); const unsigned int lcore_id = rte_lcore_id(); struct power_wait_status *s; uint64_t cur_value; @@ -109,10 +161,8 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc, * versions support this instruction natively. */ - /* set address for UMONITOR */ - asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7;" - : - : "D"(pmc->addr)); + /* set address for mmonitor */ + power_monitor_ops.mmonitor(pmc->addr); /* now that we've put this address into monitor, we can unlock */ rte_spinlock_unlock(&s->lock); @@ -123,11 +173,8 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc, if (pmc->fn(cur_value, pmc->opaque) != 0) goto end; - /* execute UMWAIT */ - asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7;" - : /* ignore rflags */ - : "D"(0), /* enter C0.2 */ - "a"(tsc_l), "d"(tsc_h)); + /* execute mwait */ + power_monitor_ops.mwait(tsc_timestamp); end: /* erase sleep address */ @@ -173,6 +220,14 @@ RTE_INIT(rte_power_intrinsics_init) { wait_multi_supported = 1; if (i.power_monitor) monitor_supported = 1; + + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MONITORX)) { /* AMD */ + power_monitor_ops.mmonitor = &amd_monitorx; + power_monitor_ops.mwait = &amd_mwaitx; + } else { /* Intel */ + power_monitor_ops.mmonitor = &intel_umonitor; + power_monitor_ops.mwait = &intel_umwait; + } } int