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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT007.mail.protection.outlook.com (10.13.177.109) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6319.24 via Frontend Transport; Thu, 20 Apr 2023 08:18:59 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Thu, 20 Apr 2023 01:18:50 -0700 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 20 Apr 2023 01:18:49 -0700 From: Viacheslav Ovsiienko To: Subject: [PATCH] net/mlx5: add timestamp ascending order error statistics Date: Thu, 20 Apr 2023 11:18:35 +0300 Message-ID: <20230420081835.19927-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT007:EE_|SJ0PR12MB6879:EE_ X-MS-Office365-Filtering-Correlation-Id: 180d83fd-3fb7-410b-62e4-08db4177e4b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199021)(40470700004)(46966006)(36840700001)(6916009)(316002)(70206006)(36756003)(186003)(70586007)(40460700003)(26005)(1076003)(16526019)(47076005)(36860700001)(6286002)(7636003)(336012)(426003)(2616005)(83380400001)(8676002)(5660300002)(41300700001)(6666004)(8936002)(82310400005)(478600001)(55016003)(7696005)(86362001)(356005)(34020700004)(40480700001)(2906002)(82740400003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2023 08:18:59.5228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 180d83fd-3fb7-410b-62e4-08db4177e4b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT007.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6879 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The ConnectX NICs support packet send scheduling on specified moment of time. Application can set the desired timestamp value in dynamic mbuf field and driver will push the special WAIT WQE to the hardware queue in order to suspend the entire queue operations till the specified time moment, then PMD pushes the regular WQE for packet sending. In the following packets the scheduling can be requested again, with different timestamps, and driver pushes WAIT WQE accordingly. The timestamps should be provided by application in ascending order as packets are queued to the hardware queue, otherwise hardware would not be able to perform scheduling correctly - it discovers the WAIT WQEs in order as they were pushed, there is no any reordering - neither in PMD, not in the NIC, and, obviously, the regular hardware can't work as time machine and wait for some elapsed moment in the past. Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_tx.h | 5 +++++ drivers/net/mlx5/mlx5_txpp.c | 12 +++++++++--- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 9eae692037..e03f1f6385 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1186,6 +1186,7 @@ struct mlx5_dev_txpp { uint64_t err_clock_queue; /* Clock Queue errors. */ uint64_t err_ts_past; /* Timestamp in the past. */ uint64_t err_ts_future; /* Timestamp in the distant future. */ + uint64_t err_ts_order; /* Timestamp not in ascending order. */ }; /* Sample ID information of eCPRI flex parser structure. */ diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index d0c6303a2d..cc8f7e98aa 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -162,6 +162,7 @@ struct mlx5_txq_data { uint16_t idx; /* Queue index. */ uint64_t rt_timemask; /* Scheduling timestamp mask. */ uint64_t ts_mask; /* Timestamp flag dynamic mask. */ + uint64_t ts_last; /* Last scheduled timestamp. */ int32_t ts_offset; /* Timestamp field dynamic offset. */ struct mlx5_dev_ctx_shared *sh; /* Shared context. */ struct mlx5_txq_stats stats; /* TX queue counters. */ @@ -1682,6 +1683,10 @@ mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq, return MLX5_TXCMP_CODE_EXIT; /* Convert the timestamp into completion to wait. */ ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *); + if (txq->ts_last && ts < txq->ts_last) + __atomic_fetch_add(&txq->sh->txpp.err_ts_order, + 1, __ATOMIC_RELAXED); + txq->ts_last = ts; wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m); sh = txq->sh; if (txq->wait_on_time) { diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index 0e1da1d5f5..5a5df2d1bb 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -29,6 +29,7 @@ static const char * const mlx5_txpp_stat_names[] = { "tx_pp_clock_queue_errors", /* Clock Queue errors. */ "tx_pp_timestamp_past_errors", /* Timestamp in the past. */ "tx_pp_timestamp_future_errors", /* Timestamp in the distant future. */ + "tx_pp_timestamp_order_errors", /* Timestamp not in ascending order. */ "tx_pp_jitter", /* Timestamp jitter (one Clock Queue completion). */ "tx_pp_wander", /* Timestamp wander (half of Clock Queue CQEs). */ "tx_pp_sync_lost", /* Scheduling synchronization lost. */ @@ -758,6 +759,7 @@ mlx5_txpp_start_service(struct mlx5_dev_ctx_shared *sh) sh->txpp.err_clock_queue = 0; sh->txpp.err_ts_past = 0; sh->txpp.err_ts_future = 0; + sh->txpp.err_ts_order = 0; /* Attach interrupt handler to process Rearm Queue completions. */ fd = mlx5_os_get_devx_channel_fd(sh->txpp.echan); ret = mlx5_os_set_nonblock_channel_fd(fd); @@ -1034,6 +1036,7 @@ int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev) __atomic_store_n(&sh->txpp.err_clock_queue, 0, __ATOMIC_RELAXED); __atomic_store_n(&sh->txpp.err_ts_past, 0, __ATOMIC_RELAXED); __atomic_store_n(&sh->txpp.err_ts_future, 0, __ATOMIC_RELAXED); + __atomic_store_n(&sh->txpp.err_ts_order, 0, __ATOMIC_RELAXED); return 0; } @@ -1221,9 +1224,12 @@ mlx5_txpp_xstats_get(struct rte_eth_dev *dev, stats[n_used + 4].value = __atomic_load_n(&sh->txpp.err_ts_future, __ATOMIC_RELAXED); - stats[n_used + 5].value = mlx5_txpp_xstats_jitter(&sh->txpp); - stats[n_used + 6].value = mlx5_txpp_xstats_wander(&sh->txpp); - stats[n_used + 7].value = sh->txpp.sync_lost; + stats[n_used + 5].value = + __atomic_load_n(&sh->txpp.err_ts_order, + __ATOMIC_RELAXED); + stats[n_used + 6].value = mlx5_txpp_xstats_jitter(&sh->txpp); + stats[n_used + 7].value = mlx5_txpp_xstats_wander(&sh->txpp); + stats[n_used + 8].value = sh->txpp.sync_lost; } return n_used + n_txpp; }