diff mbox series

[v3,02/10] net/cpfl: support hairpin queue capbility get

Message ID	20230519073116.56749-3-beilei.xing@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	Qi Zhang
Headers	From: beilei.xing@intel.com To: jingjing.wu@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>, Xiao Wang <xiao.w.wang@intel.com> Subject: [PATCH v3 02/10] net/cpfl: support hairpin queue capbility get Date: Fri, 19 May 2023 07:31:08 +0000 Message-Id: <20230519073116.56749-3-beilei.xing@intel.com> In-Reply-To: <20230519073116.56749-1-beilei.xing@intel.com> References: <20230519051055.106893-1-beilei.xing@intel.com> <20230519073116.56749-1-beilei.xing@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	net/cpfl: add hairpin queue support \| [v3,00/10] net/cpfl: add hairpin queue support [v3,01/10] net/cpfl: refine structures [v3,02/10] net/cpfl: support hairpin queue capbility get [v3,03/10] common/idpf: support queue groups add/delete [v3,04/10] net/cpfl: add haipin queue group during vport init [v3,05/10] net/cpfl: support hairpin queue setup and release [v3,06/10] net/cpfl: support hairpin queue configuration [v3,07/10] net/cpfl: support hairpin queue start/stop [v3,08/10] net/cpfl: enable write back based on ITR expire [v3,09/10] net/cpfl: support peer ports get [v3,10/10] net/cpfl: support hairpin bind/unbind

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Xing, Beilei May 19, 2023, 7:31 a.m. UTC

  From: Beilei Xing <beilei.xing@intel.com>

This patch adds hairpin_cap_get ops support.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Mingxia Liu <mingxia.liu@intel.com>
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
 drivers/net/cpfl/cpfl_ethdev.c | 13 +++++++++++++
 drivers/net/cpfl/cpfl_rxtx.h   |  4 ++++
 2 files changed, 17 insertions(+)

Comments

Jingjing Wu May 24, 2023, 2:30 p.m. UTC | #1

> -----Original Message-----
> From: Xing, Beilei <beilei.xing@intel.com>
> Sent: Friday, May 19, 2023 3:31 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; Liu, Mingxia <mingxia.liu@intel.com>; Xing, Beilei
> <beilei.xing@intel.com>; Wang, Xiao W <xiao.w.wang@intel.com>
> Subject: [PATCH v3 02/10] net/cpfl: support hairpin queue capbility get
> 
> From: Beilei Xing <beilei.xing@intel.com>
> 
> This patch adds hairpin_cap_get ops support.
> 
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> Signed-off-by: Mingxia Liu <mingxia.liu@intel.com>
> Signed-off-by: Beilei Xing <beilei.xing@intel.com>
> ---
>  drivers/net/cpfl/cpfl_ethdev.c | 13 +++++++++++++
>  drivers/net/cpfl/cpfl_rxtx.h   |  4 ++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
> index e587155db6..b6fd0b05d0 100644
> --- a/drivers/net/cpfl/cpfl_ethdev.c
> +++ b/drivers/net/cpfl/cpfl_ethdev.c
> @@ -154,6 +154,18 @@ cpfl_dev_link_update(struct rte_eth_dev *dev,
>  	return rte_eth_linkstatus_set(dev, &new_link);
>  }
> 
> +static int
> +cpfl_hairpin_cap_get(__rte_unused struct rte_eth_dev *dev,
> +		     struct rte_eth_hairpin_cap *cap)
> +{
> +	cap->max_nb_queues = CPFL_MAX_P2P_NB_QUEUES;
> +	cap->max_rx_2_tx = CPFL_MAX_HAIRPINQ_RX_2_TX;
> +	cap->max_tx_2_rx = CPFL_MAX_HAIRPINQ_TX_2_RX;
> +	cap->max_nb_desc = CPFL_MAX_HAIRPINQ_NB_DESC;
> +
Is that better to check if  p2p queue group is added successfully and then return success?

diff mbox series

Patch

diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index e587155db6..b6fd0b05d0 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -154,6 +154,18 @@  cpfl_dev_link_update(struct rte_eth_dev *dev,
 	return rte_eth_linkstatus_set(dev, &new_link);
 }
 
+static int
+cpfl_hairpin_cap_get(__rte_unused struct rte_eth_dev *dev,
+		     struct rte_eth_hairpin_cap *cap)
+{
+	cap->max_nb_queues = CPFL_MAX_P2P_NB_QUEUES;
+	cap->max_rx_2_tx = CPFL_MAX_HAIRPINQ_RX_2_TX;
+	cap->max_tx_2_rx = CPFL_MAX_HAIRPINQ_TX_2_RX;
+	cap->max_nb_desc = CPFL_MAX_HAIRPINQ_NB_DESC;
+
+	return 0;
+}
+
 static int
 cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 {
@@ -885,6 +897,7 @@  static const struct eth_dev_ops cpfl_eth_dev_ops = {
 	.xstats_get			= cpfl_dev_xstats_get,
 	.xstats_get_names		= cpfl_dev_xstats_get_names,
 	.xstats_reset			= cpfl_dev_xstats_reset,
+	.hairpin_cap_get		= cpfl_hairpin_cap_get,
 };
 
 static int
diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h
index bfb9ad97bd..b2b3537d10 100644
--- a/drivers/net/cpfl/cpfl_rxtx.h
+++ b/drivers/net/cpfl/cpfl_rxtx.h
@@ -13,6 +13,10 @@ 
 #define CPFL_MIN_RING_DESC	32
 #define CPFL_MAX_RING_DESC	4096
 #define CPFL_DMA_MEM_ALIGN	4096
+#define CPFL_MAX_HAIRPINQ_RX_2_TX	1
+#define CPFL_MAX_HAIRPINQ_TX_2_RX	1
+#define CPFL_MAX_HAIRPINQ_NB_DESC	1024
+#define CPFL_MAX_P2P_NB_QUEUES		16
 /* Base address of the HW descriptor ring should be 128B aligned. */
 #define CPFL_RING_BASE_ALIGN	128