From patchwork Thu May 25 09:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 127410 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F69542B9A; Thu, 25 May 2023 12:10:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5FE0642D69; Thu, 25 May 2023 12:10:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B884B410F9 for ; Thu, 25 May 2023 12:09:57 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34PA2UjQ020269 for ; Thu, 25 May 2023 03:09:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0GiTkWCZQ0JJs8iGB/nny2WYlrJmKP7MD9Qe2wcYG1A=; b=SX7fduDdyLzb4t1E90mtckfE4LVx79x03G6DW7+abbGua55g5pCrB3rAVi74FtOQdpwS wMh30QaUIV9ME2RWczyB4U2jcvuTjuLyQnp2uDuAo2Ads8ZlJKXoDD+EhI3+K+4dkTXb uVmJ6vj6q4GmHqlXct00aPQ/+wSHc9G5PXSRLYB+tHsNwt/nq6Q9QWaEj0V9ipcPnVSW eGD2XwV1tqF5jET5skZ08+YhyExORxvgTB9bKcJHhXdLJDSDsIjmQbynfIH50V2gDS8q wgUZTCuDKx02ToHgouc2A2VQv1jN1sCBkmHhYiCyY3p4BE1/6W3RHWbkng79BpM5SZ1O sw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qt5jng0kq-16 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 25 May 2023 03:09:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 25 May 2023 03:09:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 25 May 2023 03:09:43 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 34ECC5B6C8D; Thu, 25 May 2023 03:00:01 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 15/32] common/cnxk: avoid STALL with dual rate on CNF95N Date: Thu, 25 May 2023 15:28:47 +0530 Message-ID: <20230525095904.3967080-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525095904.3967080-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> <20230525095904.3967080-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: jMnfh1AkV0OHhya_1ozcmmnaJsmblR-Z X-Proofpoint-GUID: jMnfh1AkV0OHhya_1ozcmmnaJsmblR-Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-25_06,2023-05-24_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Due to errata RED_ALGO STALL with dual shaper rate will hangs on platforms CNF95N and CNF95O. Set READ_ALGO to DISCARD with dual shaper rate on CNF95N and CNF95O. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_tm_utils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 9ede1bebe7..3840d6d457 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -1267,7 +1267,8 @@ roc_nix_tm_shaper_default_red_algo(struct roc_nix_tm_node *node, tm_node->red_algo = roc_prof->red_algo; /* C0 doesn't support STALL when both PIR & CIR are enabled */ - if (roc_model_is_cn96_cx()) { + if (roc_model_is_cn96_cx() || roc_model_is_cnf95xxn_a0() || roc_model_is_cnf95xxo_a0() || + roc_model_is_cnf95xxn_a1() || roc_model_is_cnf95xxn_b0()) { nix_tm_shaper_conf_get(profile, &cir, &pir); if (pir.rate && cir.rate)