From patchwork Thu May 25 09:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 127434 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3B0942B9A; Thu, 25 May 2023 12:38:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C83642D5C; Thu, 25 May 2023 12:38:30 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E951A42D3B for ; Thu, 25 May 2023 12:38:28 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34PA2X1N020293 for ; Thu, 25 May 2023 03:38:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jkd+9g2j9Vo2n/Oh425aiK2uubTeIQC/7skbTG3/oMw=; b=VFrW3cCfgGB7D+k68QBEvHnWBxdCsgfZ2asawUAq0y61U6zGc2HteRrfRvDxFlc5g7lL oQehmJ23jyRx5OzG8LzAtbQWyPp6m6ua/BE9fFQ6M+O90XNZGLXNaVmkTxzI01aaEJKn Mftqp9pdI+G7Q4tPLvTzikbT9HbA0oJwVQB1rcOlD31iQVRmua35C1ygcWmC0cdUteRD +/6jW4oC7ViAySJ0wOqwE+3Wc2mqtFxcsUCr/XFCQU9xls65tFz+RrYqZiWH6/fyzbph 6hgSDQctSBELOR6ENblZAESog7Nfv7XfzchrEqOmTfRXj1NumpMOx0g6zpafpoPGVkVr 3g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qt5jng44u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 25 May 2023 03:38:27 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 25 May 2023 03:38:26 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 25 May 2023 03:38:26 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 1F1895B6E9E; Thu, 25 May 2023 03:00:36 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 27/32] common/cnxk: configure PFC on SPB aura Date: Thu, 25 May 2023 15:28:59 +0530 Message-ID: <20230525095904.3967080-27-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525095904.3967080-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> <20230525095904.3967080-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Gjh_S92t39N-rx2Mjc_84VTALD4S0iWa X-Proofpoint-GUID: Gjh_S92t39N-rx2Mjc_84VTALD4S0iWa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-25_06,2023-05-24_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori A RQ can be configured with lpb_aura and spb_aura at the same time and both can contribute to generate aura based back pressure from NIX to RPM. But currently PFC configuration are applied on lpb_aura only and spb_aura does not contribute to create back pressure. Patch adds support for the same. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_fc.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 548854952b..f60e546c01 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -198,6 +198,7 @@ struct roc_nix_fc_cfg { uint16_t cq_drop; bool enable; uint64_t pool; + uint64_t spb_pool; uint64_t pool_drop_pct; } rq_cfg; diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 21e3b7d5bd..44eade5ba6 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -303,6 +303,12 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, fc_cfg->rq_cfg.tc, pool_drop_pct); + if (rq->spb_ena) { + roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.spb_pool, + fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, + fc_cfg->rq_cfg.tc, pool_drop_pct); + } + if (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle) roc_nix_fc_npa_bp_cfg(roc_nix, roc_nix->meta_aura_handle, fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp,