From patchwork Mon May 29 09:25:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 127661 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E141442BD1; Mon, 29 May 2023 11:25:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D16C5410DD; Mon, 29 May 2023 11:25:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1D5AA410D7 for ; Mon, 29 May 2023 11:25:53 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34SN0E68006357 for ; Mon, 29 May 2023 02:25:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Wh+4dNJPN9G9N6j7Vx26JZDc52jYGTR6h7Opj4n/wGw=; b=ezofiwBkwY9jewr95z51wd7h3UHgmMf1gvnaW/Aldwq2jtDp28pUrZtEGn/jxoMP7w/O NV2l13+EGp0XrYopIyDPxjVMkaMVeLfWTHYkk/hk++slGmLFIn6NFBz388I3w5e60IK5 zgMnPfq+CNAJrltJBj9po/iYNWnApZEYreBN9gFdjb2WO3DfF+S4THdR4YYZYL1RUUsZ Jitf5LTkxCyz4w1I7u8NhmzWH+tQzUPcwgsIKEXKBPf8VRiiMudocW7sXNWXCIUnPxLv agL+yDOgNVcEqLe+7FyEzROXGPXGigRpXEb/2eWG8SWRmh/rqXaArrq27MM9fZXEuACQ wA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3quf7pdr7y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 29 May 2023 02:25:53 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 29 May 2023 02:25:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 29 May 2023 02:25:51 -0700 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 14B113F7053; Mon, 29 May 2023 02:25:47 -0700 (PDT) From: Ashwin Sekhar T K To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ashwin Sekhar T K , "Pavan Nikhilesh" CC: , , , , Subject: [PATCH v2 1/2] mempool/cnxk: fix indefinite wait in batch alloc Date: Mon, 29 May 2023 14:55:44 +0530 Message-ID: <20230529092545.959180-1-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230526134507.885354-1-asekhar@marvell.com> References: <20230526134507.885354-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZRyeLf8LTFHnP7upqzdV4rQU0wXTD1hQ X-Proofpoint-ORIG-GUID: ZRyeLf8LTFHnP7upqzdV4rQU0wXTD1hQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-29_06,2023-05-25_03,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Avoid waiting indefinitely when counting batch allocated pointers by adding a wait timeout. Fixes: 50d08d3934ec ("common/cnxk: fix batch alloc completion poll logic") Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.h | 15 +++++++++------ drivers/mempool/cnxk/cn10k_mempool_ops.c | 3 ++- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index 21608a40d9..d3caa71586 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -241,19 +241,23 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, } static inline void -roc_npa_batch_alloc_wait(uint64_t *cache_line) +roc_npa_batch_alloc_wait(uint64_t *cache_line, unsigned int wait_us) { + const uint64_t ticks = (uint64_t)wait_us * plt_tsc_hz() / (uint64_t)1E6; + const uint64_t start = plt_tsc_cycles(); + /* Batch alloc status code is updated in bits [5:6] of the first word * of the 128 byte cache line. */ while (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x3) == ALLOC_CCODE_INVAL) - ; + if (wait_us && (plt_tsc_cycles() - start) >= ticks) + break; } static inline unsigned int roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num, - unsigned int do_wait) + unsigned int wait_us) { unsigned int count, i; @@ -267,8 +271,7 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num, status = (struct npa_batch_alloc_status_s *)&aligned_buf[i]; - if (do_wait) - roc_npa_batch_alloc_wait(&aligned_buf[i]); + roc_npa_batch_alloc_wait(&aligned_buf[i], wait_us); count += status->count; } @@ -293,7 +296,7 @@ roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf, status = (struct npa_batch_alloc_status_s *)&aligned_buf[i]; - roc_npa_batch_alloc_wait(&aligned_buf[i]); + roc_npa_batch_alloc_wait(&aligned_buf[i], 0); line_count = status->count; diff --git a/drivers/mempool/cnxk/cn10k_mempool_ops.c b/drivers/mempool/cnxk/cn10k_mempool_ops.c index ba826f0f01..ff0015d8de 100644 --- a/drivers/mempool/cnxk/cn10k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn10k_mempool_ops.c @@ -9,6 +9,7 @@ #define BATCH_ALLOC_SZ ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS #define BATCH_OP_DATA_TABLE_MZ_NAME "batch_op_data_table_mz" +#define BATCH_ALLOC_WAIT_US 5 enum batch_op_status { BATCH_ALLOC_OP_NOT_ISSUED = 0, @@ -178,7 +179,7 @@ cn10k_mempool_get_count(const struct rte_mempool *mp) if (mem->status == BATCH_ALLOC_OP_ISSUED) count += roc_npa_aura_batch_alloc_count( - mem->objs, BATCH_ALLOC_SZ, 1); + mem->objs, BATCH_ALLOC_SZ, BATCH_ALLOC_WAIT_US); if (mem->status == BATCH_ALLOC_OP_DONE) count += mem->sz;