From patchwork Wed May 31 10:18:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 127766 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ABE5742BF0; Wed, 31 May 2023 12:44:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF78842D70; Wed, 31 May 2023 12:43:40 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 68DA642D52 for ; Wed, 31 May 2023 12:43:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685529815; x=1717065815; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lvfUIfxFrq74/11z85tmSj06FRDW2G6ma7q0EZpeg/U=; b=kJcQezsv1G8X+EVwbbF3uazWO0UqLvmnWRN1M+ks5wpMHEKvlKdhdmRt 0Hu8NsduZXOEBFk+uUWIzyzFE5Ey79XLT9nZVxPMkOntRBSwVNHscOlBk +5dqfAwATrv6+bDbsrs09e674iNc6WAjjjb4c324Nm6MY3cJ3a8pgnQuM EhnJ4fT3rZfaPqNYGqoLa2ma7ZRQ3rr+eNOK/lPrPzYl7RWrxnS/bSxI3 6rY8Jfzm5Xg/mO9xX1NGRrWhbSOJ+JSuSK2waWSgLaD8mcXqJCTzjIHet eNaypyxPRqA8mUAXpv4JGq7OGWmo1diwGTgEYlAh2oFGiQ+8JyoQFqzZP Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="354045048" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="354045048" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 03:43:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="881129661" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="881129661" Received: from dpdk-beileix-3.sh.intel.com ([10.67.110.253]) by orsmga005.jf.intel.com with ESMTP; 31 May 2023 03:43:32 -0700 From: beilei.xing@intel.com To: jingjing.wu@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing , Xiao Wang Subject: [PATCH v5 12/13] net/cpfl: support peer ports get Date: Wed, 31 May 2023 10:18:52 +0000 Message-Id: <20230531101853.20468-13-beilei.xing@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230531101853.20468-1-beilei.xing@intel.com> References: <20230526073850.101079-1-beilei.xing@intel.com> <20230531101853.20468-1-beilei.xing@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Beilei Xing This patch supports get hairpin peer ports. Signed-off-by: Xiao Wang Signed-off-by: Beilei Xing --- drivers/net/cpfl/cpfl_ethdev.c | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 850f1c0bc6..9fc7d3401f 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -1080,6 +1080,45 @@ cpfl_dev_close(struct rte_eth_dev *dev) return 0; } +static int +cpfl_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, + size_t len, uint32_t tx) +{ + struct cpfl_vport *cpfl_vport = + (struct cpfl_vport *)dev->data->dev_private; + struct idpf_tx_queue *txq; + struct idpf_rx_queue *rxq; + struct cpfl_tx_queue *cpfl_txq; + struct cpfl_rx_queue *cpfl_rxq; + int i, j; + + if (len <= 0) + return -EINVAL; + + if (cpfl_vport->p2p_q_chunks_info == NULL) + return -ENOTSUP; + + if (tx > 0) { + for (i = cpfl_vport->nb_data_txq, j = 0; i < dev->data->nb_tx_queues; i++, j++) { + txq = dev->data->tx_queues[i]; + if (txq == NULL) + return -EINVAL; + cpfl_txq = (struct cpfl_tx_queue *)txq; + peer_ports[j] = cpfl_txq->hairpin_info.peer_rxp; + } + } else if (tx == 0) { + for (i = cpfl_vport->nb_data_rxq, j = 0; i < dev->data->nb_rx_queues; i++, j++) { + rxq = dev->data->rx_queues[i]; + if (rxq == NULL) + return -EINVAL; + cpfl_rxq = (struct cpfl_rx_queue *)rxq; + peer_ports[j] = cpfl_rxq->hairpin_info.peer_txp; + } + } + + return j; +} + static const struct eth_dev_ops cpfl_eth_dev_ops = { .dev_configure = cpfl_dev_configure, .dev_close = cpfl_dev_close, @@ -1109,6 +1148,7 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .hairpin_cap_get = cpfl_hairpin_cap_get, .rx_hairpin_queue_setup = cpfl_rx_hairpin_queue_setup, .tx_hairpin_queue_setup = cpfl_tx_hairpin_queue_setup, + .hairpin_get_peer_ports = cpfl_hairpin_get_peer_ports, }; static int