[v7,14/14] doc: update the doc of CPFL PMD

Message ID 20230531130450.26380-15-beilei.xing@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series net/cpfl: add hairpin queue support |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/Intel-compilation fail Compilation issues
ci/intel-Testing fail Testing issues

Commit Message

Xing, Beilei May 31, 2023, 1:04 p.m. UTC
  From: Beilei Xing <beilei.xing@intel.com>

Update cpfl.rst to clarify hairpin support.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
 doc/guides/nics/cpfl.rst | 7 +++++++
 1 file changed, 7 insertions(+)
  

Patch

diff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst
index d25db088eb..8d5c3082e4 100644
--- a/doc/guides/nics/cpfl.rst
+++ b/doc/guides/nics/cpfl.rst
@@ -106,3 +106,10 @@  The paths are chosen based on 2 conditions:
   A value "P" means the offload feature is not supported by vector path.
   If any not supported features are used, cpfl vector PMD is disabled
   and the scalar paths are chosen.
+
+Hairpin queue
+~~~~~~~~~~~~~
+
+ E2100 Series can loopback packets from RX port to TX port, this feature is
+ called port-to-port or hairpin.
+ Currently, the PMD only supports single port hairpin.