From patchwork Mon Jun 5 08:21:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 128097 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92CC942C34; Mon, 5 Jun 2023 10:21:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD739410EE; Mon, 5 Jun 2023 10:21:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B46DC40ED6 for ; Mon, 5 Jun 2023 10:21:31 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 354LJii5027952; Mon, 5 Jun 2023 01:21:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=4Oo8/WgJWqH0LU2mzUtckT0eXM6T++Wg7R6gs4/bmfw=; b=fxZrRop0sV+Xosx3hIsYONwo3G9mVPTymrYaFUAm+/ys2/yyYEF5Y0I93035OPF7Zh7M zPAeeve5wQZOw6wf/fCJMP7OxHKFe822jPl7e1oK/6PC6AEkXNlhYhlEBYeQsakZjKzy S38FL9OoNDQlbJHqzDQB0xYO90bbQFp7t8XVubAWCNdXwBrbVHj/ETdAxlosVA789Seq moA9c/POWCPEZcTe5CH/9+XvtyysHUe2nDmKep0g+Nq7Ezo/y3Ev8SfKekFV28EAArWH 8aZEuU0U8W98obCtS+YHrz1TF7E5Ukge2FnWXxlGh9MtfZMbmFOO+VMQMSvFkGZddgHQ HA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r02vpdsft-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 05 Jun 2023 01:21:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 5 Jun 2023 01:21:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 5 Jun 2023 01:21:28 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 312333F706B; Mon, 5 Jun 2023 01:21:26 -0700 (PDT) From: Nithin Dabilpuram To: Radu Nicolau , Akhil Goyal CC: , , Nithin Dabilpuram Subject: [PATCH 2/3] examples/ipsec-secgw: skip Rx scatter for HW reassembly Date: Mon, 5 Jun 2023 13:51:21 +0530 Message-ID: <20230605082122.422934-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230605082122.422934-1-ndabilpuram@marvell.com> References: <20230605082122.422934-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qfW3ibyD2D0eS_1iMeDEa7Wxh9n9aKKw X-Proofpoint-ORIG-GUID: qfW3ibyD2D0eS_1iMeDEa7Wxh9n9aKKw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-03_08,2023-06-02_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When HW reassembly is enabled, currently both Rx scatter and Tx multi-segs ethdev offload flags are enabled. Tx multi-seg is needed to Tx the reassembled pkt but Rx scatter is not needed as reassembly should be self sufficient offload flag. Hence remove it and only enable Tx multi-segs when HW reassembly is enabled. Signed-off-by: Nithin Dabilpuram --- examples/ipsec-secgw/sa.c | 1 - 1 file changed, 1 deletion(-) diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c index 5f5d2685f6..a25b4e2de7 100644 --- a/examples/ipsec-secgw/sa.c +++ b/examples/ipsec-secgw/sa.c @@ -1850,7 +1850,6 @@ sa_check_offloads(uint16_t port_id, uint64_t *rx_offloads, && rule->portid == port_id) *rx_offloads |= RTE_ETH_RX_OFFLOAD_SECURITY; if (IS_HW_REASSEMBLY_EN(rule->flags)) { - *rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER; *tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS; *hw_reassembly = 1; }