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Tue, 13 Jun 2023 22:52:39 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 1/2] net/mlx5: align implementation with modify API Date: Wed, 14 Jun 2023 08:52:33 +0300 Message-ID: <20230614055234.2322466-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614055234.2322466-1-michaelba@nvidia.com> References: <20230614055234.2322466-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT060:EE_|BY5PR12MB4322:EE_ X-MS-Office365-Filtering-Correlation-Id: 09d0ced4-0502-46ac-718a-08db6c9b92e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MoolPDiixRX6X9a0Lwq1T0J+QV8N0rVBB7H0lMdoxEW2He7mSF8WNIzaE8oNlML+uaSvVCxFonB6zCu6q7aidf5CTZUeRuCFnzSbiPacR5QSecXzRzL+/7xV4x/fyK4+4opQUfH5csnK2/FK4r6W00NyvyQWyL5eF05tOnYhjOSuPEZTtsKT8vuE9ElzUMIxqTMGAAd9UPlnRumalO4CrKVXf4plRqiXEj4u56bG120rGjLMPB3kq5+x+Oqnva6eJtN/dOt14NZgUPiHDJEK5AaNRwcNRs3RbYpb6EtV8jkPaGQ1ShIh2fyjsSeJQAnou98B2Qs3kzBUY/CWt3XgdwgXJ/eGJkaJTXpdL2RiU1+i+0AEVbpbkMyW2DUXpY1PYmBJo3DHdKFbXwK8YRXd3D6oOBIlnDMlQn13JOrJEOLRkn2t6NZT8g8Z96EvttAZJvy/QDGn7lb+KMMN9bZJvoUSzw+tEtwjEFhANyr/M/7fH1WN+MmXUJrWW1MoBzkjvvY/SffMBRMVk7A0KYcHN2bV61biqpE1nqZSgWQsVU1spyVrnStacLvCcgGwtGLoR5noEbXSci697A/xX9tYI3MPOs9fI6/8Rou1FgvaZ/yeWPQ2BPwkS3XObPQbSrRNPgEwHSBrYJ67l7um0DNshroXsiHUrSNrocRi7ll/7aanpxeDAKv8JBVf56oNaaxpLJWHtfMGLD3j4xjDOo+LY8/PRL1YFXySdhuDclq4VJg= X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Although the old API still work, this patch move all internal API usage to use "tag_index". Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow.h | 12 +++++++++ drivers/net/mlx5/mlx5_flow_dv.c | 18 +++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 47 ++++++++++++++++++++++++++------- 3 files changed, 67 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 02e33c7fb3..568dae751e 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1108,6 +1108,18 @@ flow_dv_fetch_field(const uint8_t *data, uint32_t size) return ret; } +static inline bool +flow_modify_field_support_tag_array(enum rte_flow_field_id field) +{ + switch (field) { + case RTE_FLOW_FIELD_TAG: + return true; + default: + break; + } + return false; +} + struct field_modify_info { uint32_t size; /* Size of field in protocol header, in bytes. */ uint32_t offset; /* Offset of field in protocol header, in bytes. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 7535500870..f6278935c1 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5291,6 +5291,15 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, ret = flow_validate_modify_field_level(dst_data, error); if (ret) return ret; + if (dst_data->tag_index && + !flow_modify_field_support_tag_array(dst_data->field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination tag index is not supported"); + if (dst_data->class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination class ID is not supported"); } if (src_data->field != RTE_FLOW_FIELD_VALUE && src_data->field != RTE_FLOW_FIELD_POINTER) { @@ -5306,6 +5315,15 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, ret = flow_validate_modify_field_level(src_data, error); if (ret) return ret; + if (src_data->tag_index && + !flow_modify_field_support_tag_array(src_data->field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source tag index is not supported"); + if (src_data->class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source class ID is not supported"); } if ((dst_data->field == src_data->field) && (dst_data->level == src_data->level)) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f17a2a0522..0c76ee7446 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3653,6 +3653,15 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, ret = flow_validate_modify_field_level(&action_conf->dst, error); if (ret) return ret; + if (action_conf->dst.tag_index && + !flow_modify_field_support_tag_array(action_conf->dst.field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination tag index is not supported"); + if (action_conf->dst.class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "destination class id is not supported"); if (mask_conf->dst.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -3667,6 +3676,15 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, "destination field mask and template are not equal"); if (action_conf->src.field != RTE_FLOW_FIELD_POINTER && action_conf->src.field != RTE_FLOW_FIELD_VALUE) { + if (action_conf->src.tag_index && + !flow_modify_field_support_tag_array(action_conf->src.field)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source tag index is not supported"); + if (action_conf->src.class_id) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "source class id is not supported"); if (mask_conf->src.level != UINT8_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -4646,12 +4664,12 @@ static const struct rte_flow_action rx_meta_copy_action = { .dst = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_B, + .tag_index = REG_B, }, .src = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .width = 32, } @@ -4665,12 +4683,14 @@ static const struct rte_flow_action rx_meta_copy_mask = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id) MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -4701,6 +4721,7 @@ static const struct rte_flow_action quota_color_inc_mask = { .dst = { .field = RTE_FLOW_FIELD_METER_COLOR, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -5824,7 +5845,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_0, + .tag_index = REG_C_0, .offset = rte_bsf32(tag_mask), }, .src = { @@ -5837,6 +5858,7 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -5848,11 +5870,11 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_A, + .tag_index = REG_A, }, .width = 32, }; @@ -5861,11 +5883,13 @@ flow_hw_create_tx_repr_tag_jump_acts_tmpl(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -6181,7 +6205,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_0, + .tag_index = REG_C_0, }, .src = { .field = RTE_FLOW_FIELD_VALUE, @@ -6193,6 +6217,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { @@ -6353,11 +6378,11 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_A, + .tag_index = REG_A, }, .width = 32, }; @@ -6366,11 +6391,13 @@ flow_hw_create_tx_default_mreg_copy_actions_template(struct rte_eth_dev *dev) .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, .level = UINT8_MAX, + .tag_index = UINT8_MAX, .offset = UINT32_MAX, }, .width = UINT32_MAX, @@ -9514,11 +9541,11 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev) .operation = RTE_FLOW_MODIFY_SET, .dst = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_C_1, + .tag_index = REG_C_1, }, .src = { .field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG, - .level = REG_A, + .tag_index = REG_A, }, .width = 32, };