[v2,06/15] pci: define some MSIX constants
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Commit Message
Define some PCI MSIX constants and use them in existing drivers.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/bus/pci/linux/pci_init.h | 18 ------------------
drivers/bus/pci/linux/pci_vfio.c | 7 ++++---
drivers/crypto/virtio/virtio_pci.c | 6 ++----
drivers/event/dlb2/pf/dlb2_main.c | 13 +++++--------
drivers/net/bnx2x/bnx2x.c | 4 ++--
drivers/net/bnx2x/bnx2x.h | 2 --
drivers/net/gve/gve_ethdev.c | 4 ++--
drivers/net/gve/gve_ethdev.h | 8 --------
drivers/net/hns3/hns3_ethdev_vf.c | 9 ++++-----
drivers/net/virtio/virtio_pci.c | 6 ++----
lib/pci/rte_pci.h | 10 ++++++++++
11 files changed, 31 insertions(+), 56 deletions(-)
Comments
> -----Original Message-----
> From: David Marchand <david.marchand@redhat.com>
> Sent: Monday, August 21, 2023 7:36 PM
> To: dev@dpdk.org
> Cc: thomas@monjalon.net; ferruh.yigit@amd.com; Xia, Chenbo
> <chenbo.xia@intel.com>; nipun.gupta@amd.com; Richardson, Bruce
> <bruce.richardson@intel.com>; Burakov, Anatoly <anatoly.burakov@intel.com>;
> Jay Zhou <jianjay.zhou@huawei.com>; McDaniel, Timothy
> <timothy.mcdaniel@intel.com>; Julien Aube <julien_dpdk@jaube.fr>; Guo,
> Junfeng <junfeng.guo@intel.com>; Jeroen de Borst <jeroendb@google.com>;
> Rushil Gupta <rushilg@google.com>; Joshua Washington <joshwash@google.com>;
> Dongdong Liu <liudongdong3@huawei.com>; Yisen Zhuang
> <yisen.zhuang@huawei.com>; Maxime Coquelin <maxime.coquelin@redhat.com>;
> Gaetan Rivet <grive@u256.net>
> Subject: [PATCH v2 06/15] pci: define some MSIX constants
>
> Define some PCI MSIX constants and use them in existing drivers.
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
> ---
> drivers/bus/pci/linux/pci_init.h | 18 ------------------
> drivers/bus/pci/linux/pci_vfio.c | 7 ++++---
> drivers/crypto/virtio/virtio_pci.c | 6 ++----
> drivers/event/dlb2/pf/dlb2_main.c | 13 +++++--------
> drivers/net/bnx2x/bnx2x.c | 4 ++--
> drivers/net/bnx2x/bnx2x.h | 2 --
> drivers/net/gve/gve_ethdev.c | 4 ++--
> drivers/net/gve/gve_ethdev.h | 8 --------
> drivers/net/hns3/hns3_ethdev_vf.c | 9 ++++-----
> drivers/net/virtio/virtio_pci.c | 6 ++----
> lib/pci/rte_pci.h | 10 ++++++++++
> 11 files changed, 31 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/bus/pci/linux/pci_init.h
> b/drivers/bus/pci/linux/pci_init.h
> index d842809ccd..a4d37c0d0a 100644
> --- a/drivers/bus/pci/linux/pci_init.h
> +++ b/drivers/bus/pci/linux/pci_init.h
> @@ -52,24 +52,6 @@ int pci_uio_ioport_unmap(struct rte_pci_ioport *p);
>
> #ifdef VFIO_PRESENT
>
> -#ifdef PCI_MSIX_TABLE_BIR
> -#define RTE_PCI_MSIX_TABLE_BIR PCI_MSIX_TABLE_BIR
> -#else
> -#define RTE_PCI_MSIX_TABLE_BIR 0x7
> -#endif
> -
> -#ifdef PCI_MSIX_TABLE_OFFSET
> -#define RTE_PCI_MSIX_TABLE_OFFSET PCI_MSIX_TABLE_OFFSET
> -#else
> -#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8
> -#endif
> -
> -#ifdef PCI_MSIX_FLAGS_QSIZE
> -#define RTE_PCI_MSIX_FLAGS_QSIZE PCI_MSIX_FLAGS_QSIZE
> -#else
> -#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff
> -#endif
> -
> /* access config space */
> int pci_vfio_read_config(const struct rte_pci_device *dev,
> void *buf, size_t len, off_t offs);
> diff --git a/drivers/bus/pci/linux/pci_vfio.c
> b/drivers/bus/pci/linux/pci_vfio.c
> index bfedbc1bed..7881b7a946 100644
> --- a/drivers/bus/pci/linux/pci_vfio.c
> +++ b/drivers/bus/pci/linux/pci_vfio.c
> @@ -120,14 +120,15 @@ pci_vfio_get_msix_bar(const struct rte_pci_device
> *dev,
> uint16_t flags;
> uint32_t reg;
>
> - /* table offset resides in the next 4 bytes */
> - if (rte_pci_read_config(dev, ®, sizeof(reg), cap_offset + 4)
> < 0) {
> + if (rte_pci_read_config(dev, ®, sizeof(reg), cap_offset +
> + RTE_PCI_MSIX_TABLE) < 0) {
> RTE_LOG(ERR, EAL,
> "Cannot read MSIX table from PCI config space!\n");
> return -1;
> }
>
> - if (rte_pci_read_config(dev, &flags, sizeof(flags), cap_offset
> + 2) < 0) {
> + if (rte_pci_read_config(dev, &flags, sizeof(flags), cap_offset
> +
> + RTE_PCI_MSIX_FLAGS) < 0) {
> RTE_LOG(ERR, EAL,
> "Cannot read MSIX flags from PCI config space!\n");
> return -1;
> diff --git a/drivers/crypto/virtio/virtio_pci.c
> b/drivers/crypto/virtio/virtio_pci.c
> index 9e340f2b0d..c9fb1087a9 100644
> --- a/drivers/crypto/virtio/virtio_pci.c
> +++ b/drivers/crypto/virtio/virtio_pci.c
> @@ -329,8 +329,6 @@ get_cfg_addr(struct rte_pci_device *dev, struct
> virtio_pci_cap *cap)
> return base + offset;
> }
>
> -#define PCI_MSIX_ENABLE 0x8000
> -
> static int
> virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)
> {
> @@ -350,8 +348,8 @@ virtio_read_caps(struct rte_pci_device *dev, struct
> virtio_crypto_hw *hw)
> */
> pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);
> if (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),
> - pos + 2) == sizeof(flags)) {
> - if (flags & PCI_MSIX_ENABLE)
> + pos + RTE_PCI_MSIX_FLAGS) == sizeof(flags)) {
> + if (flags & RTE_PCI_MSIX_FLAGS_ENABLE)
> hw->use_msix = VIRTIO_MSIX_ENABLED;
> else
> hw->use_msix = VIRTIO_MSIX_DISABLED;
> diff --git a/drivers/event/dlb2/pf/dlb2_main.c
> b/drivers/event/dlb2/pf/dlb2_main.c
> index 1a229baee0..c6606a9bee 100644
> --- a/drivers/event/dlb2/pf/dlb2_main.c
> +++ b/drivers/event/dlb2/pf/dlb2_main.c
> @@ -44,9 +44,6 @@
> #define DLB2_PCI_PRI_CTRL_ENABLE 0x1
> #define DLB2_PCI_PRI_ALLOC_REQ 0xC
> #define DLB2_PCI_PRI_CTRL 0x4
> -#define DLB2_PCI_MSIX_FLAGS 0x2
> -#define DLB2_PCI_MSIX_FLAGS_ENABLE 0x8000
> -#define DLB2_PCI_MSIX_FLAGS_MASKALL 0x4000
> #define DLB2_PCI_ERR_ROOT_STATUS 0x30
> #define DLB2_PCI_ERR_COR_STATUS 0x10
> #define DLB2_PCI_ERR_UNCOR_STATUS 0x4
> @@ -483,10 +480,10 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
>
> msix_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX);
> if (msix_cap_offset >= 0) {
> - off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;
> + off = msix_cap_offset + RTE_PCI_MSIX_FLAGS;
> if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
> - cmd |= DLB2_PCI_MSIX_FLAGS_ENABLE;
> - cmd |= DLB2_PCI_MSIX_FLAGS_MASKALL;
> + cmd |= RTE_PCI_MSIX_FLAGS_ENABLE;
> + cmd |= RTE_PCI_MSIX_FLAGS_MASKALL;
> if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
> DLB2_LOG_ERR("[%s()] failed to write msix flags\n",
> __func__);
> @@ -494,9 +491,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
> }
> }
>
> - off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;
> + off = msix_cap_offset + RTE_PCI_MSIX_FLAGS;
> if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
> - cmd &= ~DLB2_PCI_MSIX_FLAGS_MASKALL;
> + cmd &= ~RTE_PCI_MSIX_FLAGS_MASKALL;
> if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
> DLB2_LOG_ERR("[%s()] failed to write msix flags\n",
> __func__);
> diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c
> index 8a97de8806..e3f14400cc 100644
> --- a/drivers/net/bnx2x/bnx2x.c
> +++ b/drivers/net/bnx2x/bnx2x.c
> @@ -9766,9 +9766,9 @@ int bnx2x_attach(struct bnx2x_softc *sc)
> if (sc->devinfo.pcie_msix_cap_reg != 0) {
> uint32_t val;
> pci_read(sc,
> - (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
> + (sc->devinfo.pcie_msix_cap_reg + RTE_PCI_MSIX_FLAGS),
> &val,
> 2);
> - sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
> + sc->igu_sb_cnt = (val & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;
> } else {
> sc->igu_sb_cnt = 1;
> }
> diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
> index 07ef0567c2..60af75d336 100644
> --- a/drivers/net/bnx2x/bnx2x.h
> +++ b/drivers/net/bnx2x/bnx2x.h
> @@ -46,8 +46,6 @@
> #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
> #define PCIM_PSTAT_D3 0x3
> #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
> -#define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
> -#define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
> #else
> #include <dev/pci/pcireg.h>
> #endif
> diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
> index 9ea5dbaeea..9b25f3036b 100644
> --- a/drivers/net/gve/gve_ethdev.c
> +++ b/drivers/net/gve/gve_ethdev.c
> @@ -613,8 +613,8 @@ pci_dev_msix_vec_count(struct rte_pci_device *pdev)
> uint16_t control;
>
> if (msix_pos > 0 && rte_pci_read_config(pdev, &control,
> sizeof(control),
> - msix_pos + PCI_MSIX_FLAGS) == sizeof(control))
> - return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
> + msix_pos + RTE_PCI_MSIX_FLAGS) == sizeof(control))
> + return (control & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;
>
> return 0;
> }
> diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
> index d604a75b7f..c47b4d454d 100644
> --- a/drivers/net/gve/gve_ethdev.h
> +++ b/drivers/net/gve/gve_ethdev.h
> @@ -15,14 +15,6 @@
> /* TODO: this is a workaround to ensure that Tx complq is enough */
> #define DQO_TX_MULTIPLIER 4
>
> -/*
> - * Following macros are derived from linux/pci_regs.h, however,
> - * we can't simply include that header here, as there is no such
> - * file for non-Linux platform.
> - */
> -#define PCI_MSIX_FLAGS 2 /* Message Control */
> -#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
> -
> #define GVE_DEFAULT_RX_FREE_THRESH 512
> #define GVE_DEFAULT_TX_FREE_THRESH 32
> #define GVE_DEFAULT_TX_RS_THRESH 32
> diff --git a/drivers/net/hns3/hns3_ethdev_vf.c
> b/drivers/net/hns3/hns3_ethdev_vf.c
> index eab5c55f5e..3729615159 100644
> --- a/drivers/net/hns3/hns3_ethdev_vf.c
> +++ b/drivers/net/hns3/hns3_ethdev_vf.c
> @@ -2,7 +2,6 @@
> * Copyright(c) 2018-2021 HiSilicon Limited.
> */
>
> -#include <linux/pci_regs.h>
> #include <rte_alarm.h>
> #include <ethdev_pci.h>
> #include <rte_io.h>
> @@ -64,18 +63,18 @@ hns3vf_enable_msix(const struct rte_pci_device *device,
> bool op)
> pos = rte_pci_find_capability(device, RTE_PCI_CAP_ID_MSIX);
> if (pos > 0) {
> ret = rte_pci_read_config(device, &control, sizeof(control),
> - pos + PCI_MSIX_FLAGS);
> + pos + RTE_PCI_MSIX_FLAGS);
> if (ret < 0) {
> PMD_INIT_LOG(ERR, "Failed to read MSIX flags");
> return -ENXIO;
> }
>
> if (op)
> - control |= PCI_MSIX_FLAGS_ENABLE;
> + control |= RTE_PCI_MSIX_FLAGS_ENABLE;
> else
> - control &= ~PCI_MSIX_FLAGS_ENABLE;
> + control &= ~RTE_PCI_MSIX_FLAGS_ENABLE;
> ret = rte_pci_write_config(device, &control, sizeof(control),
> - pos + PCI_MSIX_FLAGS);
> + pos + RTE_PCI_MSIX_FLAGS);
> if (ret < 0) {
> PMD_INIT_LOG(ERR, "failed to write MSIX flags");
> return -ENXIO;
> diff --git a/drivers/net/virtio/virtio_pci.c
> b/drivers/net/virtio/virtio_pci.c
> index 81d5dd0a4a..cdffef267f 100644
> --- a/drivers/net/virtio/virtio_pci.c
> +++ b/drivers/net/virtio/virtio_pci.c
> @@ -24,8 +24,6 @@
>
> struct virtio_pci_internal virtio_pci_internal[RTE_MAX_ETHPORTS];
>
> -#define PCI_MSIX_ENABLE 0x8000
> -
> static enum virtio_msix_status
> vtpci_msix_detect(struct rte_pci_device *dev)
> {
> @@ -34,8 +32,8 @@ vtpci_msix_detect(struct rte_pci_device *dev)
>
> pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);
> if (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),
> - pos + 2) == sizeof(flags)) {
> - if (flags & PCI_MSIX_ENABLE)
> + pos + RTE_PCI_MSIX_FLAGS) == sizeof(flags)) {
> + if (flags & RTE_PCI_MSIX_FLAGS_ENABLE)
> return VIRTIO_MSIX_ENABLED;
> else
> return VIRTIO_MSIX_DISABLED;
> diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> index 5a04a5a4b5..41dc725cc4 100644
> --- a/lib/pci/rte_pci.h
> +++ b/lib/pci/rte_pci.h
> @@ -51,6 +51,16 @@ extern "C" {
> #define RTE_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
> #define RTE_PCI_CAP_SIZEOF 4
>
> +/* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */
> +#define RTE_PCI_MSIX_FLAGS 2 /* Message Control */
> +#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */
> +#define RTE_PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for
> this function */
> +#define RTE_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
> +
> +#define RTE_PCI_MSIX_TABLE 4 /* Table offset */
> +#define RTE_PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */
> +#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified
> BAR */
> +
> /* PCI Express capability registers */
> #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
>
> --
> 2.41.0
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>
@@ -52,24 +52,6 @@ int pci_uio_ioport_unmap(struct rte_pci_ioport *p);
#ifdef VFIO_PRESENT
-#ifdef PCI_MSIX_TABLE_BIR
-#define RTE_PCI_MSIX_TABLE_BIR PCI_MSIX_TABLE_BIR
-#else
-#define RTE_PCI_MSIX_TABLE_BIR 0x7
-#endif
-
-#ifdef PCI_MSIX_TABLE_OFFSET
-#define RTE_PCI_MSIX_TABLE_OFFSET PCI_MSIX_TABLE_OFFSET
-#else
-#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8
-#endif
-
-#ifdef PCI_MSIX_FLAGS_QSIZE
-#define RTE_PCI_MSIX_FLAGS_QSIZE PCI_MSIX_FLAGS_QSIZE
-#else
-#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff
-#endif
-
/* access config space */
int pci_vfio_read_config(const struct rte_pci_device *dev,
void *buf, size_t len, off_t offs);
@@ -120,14 +120,15 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev,
uint16_t flags;
uint32_t reg;
- /* table offset resides in the next 4 bytes */
- if (rte_pci_read_config(dev, ®, sizeof(reg), cap_offset + 4) < 0) {
+ if (rte_pci_read_config(dev, ®, sizeof(reg), cap_offset +
+ RTE_PCI_MSIX_TABLE) < 0) {
RTE_LOG(ERR, EAL,
"Cannot read MSIX table from PCI config space!\n");
return -1;
}
- if (rte_pci_read_config(dev, &flags, sizeof(flags), cap_offset + 2) < 0) {
+ if (rte_pci_read_config(dev, &flags, sizeof(flags), cap_offset +
+ RTE_PCI_MSIX_FLAGS) < 0) {
RTE_LOG(ERR, EAL,
"Cannot read MSIX flags from PCI config space!\n");
return -1;
@@ -329,8 +329,6 @@ get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
return base + offset;
}
-#define PCI_MSIX_ENABLE 0x8000
-
static int
virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)
{
@@ -350,8 +348,8 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw)
*/
pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);
if (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),
- pos + 2) == sizeof(flags)) {
- if (flags & PCI_MSIX_ENABLE)
+ pos + RTE_PCI_MSIX_FLAGS) == sizeof(flags)) {
+ if (flags & RTE_PCI_MSIX_FLAGS_ENABLE)
hw->use_msix = VIRTIO_MSIX_ENABLED;
else
hw->use_msix = VIRTIO_MSIX_DISABLED;
@@ -44,9 +44,6 @@
#define DLB2_PCI_PRI_CTRL_ENABLE 0x1
#define DLB2_PCI_PRI_ALLOC_REQ 0xC
#define DLB2_PCI_PRI_CTRL 0x4
-#define DLB2_PCI_MSIX_FLAGS 0x2
-#define DLB2_PCI_MSIX_FLAGS_ENABLE 0x8000
-#define DLB2_PCI_MSIX_FLAGS_MASKALL 0x4000
#define DLB2_PCI_ERR_ROOT_STATUS 0x30
#define DLB2_PCI_ERR_COR_STATUS 0x10
#define DLB2_PCI_ERR_UNCOR_STATUS 0x4
@@ -483,10 +480,10 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
msix_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX);
if (msix_cap_offset >= 0) {
- off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;
+ off = msix_cap_offset + RTE_PCI_MSIX_FLAGS;
if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
- cmd |= DLB2_PCI_MSIX_FLAGS_ENABLE;
- cmd |= DLB2_PCI_MSIX_FLAGS_MASKALL;
+ cmd |= RTE_PCI_MSIX_FLAGS_ENABLE;
+ cmd |= RTE_PCI_MSIX_FLAGS_MASKALL;
if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
DLB2_LOG_ERR("[%s()] failed to write msix flags\n",
__func__);
@@ -494,9 +491,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
}
}
- off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;
+ off = msix_cap_offset + RTE_PCI_MSIX_FLAGS;
if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
- cmd &= ~DLB2_PCI_MSIX_FLAGS_MASKALL;
+ cmd &= ~RTE_PCI_MSIX_FLAGS_MASKALL;
if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
DLB2_LOG_ERR("[%s()] failed to write msix flags\n",
__func__);
@@ -9766,9 +9766,9 @@ int bnx2x_attach(struct bnx2x_softc *sc)
if (sc->devinfo.pcie_msix_cap_reg != 0) {
uint32_t val;
pci_read(sc,
- (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
+ (sc->devinfo.pcie_msix_cap_reg + RTE_PCI_MSIX_FLAGS), &val,
2);
- sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
+ sc->igu_sb_cnt = (val & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;
} else {
sc->igu_sb_cnt = 1;
}
@@ -46,8 +46,6 @@
#define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
#define PCIM_PSTAT_D3 0x3
#define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
-#define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
-#define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
#else
#include <dev/pci/pcireg.h>
#endif
@@ -613,8 +613,8 @@ pci_dev_msix_vec_count(struct rte_pci_device *pdev)
uint16_t control;
if (msix_pos > 0 && rte_pci_read_config(pdev, &control, sizeof(control),
- msix_pos + PCI_MSIX_FLAGS) == sizeof(control))
- return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
+ msix_pos + RTE_PCI_MSIX_FLAGS) == sizeof(control))
+ return (control & RTE_PCI_MSIX_FLAGS_QSIZE) + 1;
return 0;
}
@@ -15,14 +15,6 @@
/* TODO: this is a workaround to ensure that Tx complq is enough */
#define DQO_TX_MULTIPLIER 4
-/*
- * Following macros are derived from linux/pci_regs.h, however,
- * we can't simply include that header here, as there is no such
- * file for non-Linux platform.
- */
-#define PCI_MSIX_FLAGS 2 /* Message Control */
-#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
-
#define GVE_DEFAULT_RX_FREE_THRESH 512
#define GVE_DEFAULT_TX_FREE_THRESH 32
#define GVE_DEFAULT_TX_RS_THRESH 32
@@ -2,7 +2,6 @@
* Copyright(c) 2018-2021 HiSilicon Limited.
*/
-#include <linux/pci_regs.h>
#include <rte_alarm.h>
#include <ethdev_pci.h>
#include <rte_io.h>
@@ -64,18 +63,18 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
pos = rte_pci_find_capability(device, RTE_PCI_CAP_ID_MSIX);
if (pos > 0) {
ret = rte_pci_read_config(device, &control, sizeof(control),
- pos + PCI_MSIX_FLAGS);
+ pos + RTE_PCI_MSIX_FLAGS);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read MSIX flags");
return -ENXIO;
}
if (op)
- control |= PCI_MSIX_FLAGS_ENABLE;
+ control |= RTE_PCI_MSIX_FLAGS_ENABLE;
else
- control &= ~PCI_MSIX_FLAGS_ENABLE;
+ control &= ~RTE_PCI_MSIX_FLAGS_ENABLE;
ret = rte_pci_write_config(device, &control, sizeof(control),
- pos + PCI_MSIX_FLAGS);
+ pos + RTE_PCI_MSIX_FLAGS);
if (ret < 0) {
PMD_INIT_LOG(ERR, "failed to write MSIX flags");
return -ENXIO;
@@ -24,8 +24,6 @@
struct virtio_pci_internal virtio_pci_internal[RTE_MAX_ETHPORTS];
-#define PCI_MSIX_ENABLE 0x8000
-
static enum virtio_msix_status
vtpci_msix_detect(struct rte_pci_device *dev)
{
@@ -34,8 +32,8 @@ vtpci_msix_detect(struct rte_pci_device *dev)
pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX);
if (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags),
- pos + 2) == sizeof(flags)) {
- if (flags & PCI_MSIX_ENABLE)
+ pos + RTE_PCI_MSIX_FLAGS) == sizeof(flags)) {
+ if (flags & RTE_PCI_MSIX_FLAGS_ENABLE)
return VIRTIO_MSIX_ENABLED;
else
return VIRTIO_MSIX_DISABLED;
@@ -51,6 +51,16 @@ extern "C" {
#define RTE_PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define RTE_PCI_CAP_SIZEOF 4
+/* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */
+#define RTE_PCI_MSIX_FLAGS 2 /* Message Control */
+#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */
+#define RTE_PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
+#define RTE_PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
+
+#define RTE_PCI_MSIX_TABLE 4 /* Table offset */
+#define RTE_PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */
+#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */
+
/* PCI Express capability registers */
#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */