From patchwork Wed Aug 23 06:29:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 130662 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 574A2430DE; Wed, 23 Aug 2023 08:29:23 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4205340ED6; Wed, 23 Aug 2023 08:29:23 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 1261C40A79 for ; Wed, 23 Aug 2023 08:29:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1692772161; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gAQ7QNY7k/JnTmzIDN/mPjaCR6pCq0IxufRAgnUMEOY=; b=TYcRLUzmzSfa1mqe5UzSGSs8o9ftWNq3AA6QCf+Db4S+sM/SyyeqKLOeV25WQqySOjLQu2 MrHi0XCTRn7weg+UhjQ+qWRZixhtMM60/qZfZONDWqHDi4Cv9u+4geJ459O96paoQ0Pz0L wcfBuzAyiiaabaNlyUZguUhy5w+S/8A= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-681-YeuxUBvCNg279cuxDhy1jQ-1; Wed, 23 Aug 2023 02:29:16 -0400 X-MC-Unique: YeuxUBvCNg279cuxDhy1jQ-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id EC56685CBE5; Wed, 23 Aug 2023 06:29:15 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.147]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3569340C6F4C; Wed, 23 Aug 2023 06:29:14 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: echaudro@redhat.com, mkp@redhat.com, qi.z.zhang@intel.com, stable@dpdk.org, Jingjing Wu , Beilei Xing , Abhijit Sinha , Declan Doherty , Radu Nicolau Subject: [PATCH v2] net/iavf: fix checksum offloading Date: Wed, 23 Aug 2023 08:29:11 +0200 Message-ID: <20230823062911.2483926-1-david.marchand@redhat.com> In-Reply-To: <20230818090351.2402519-1-david.marchand@redhat.com> References: <20230818090351.2402519-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org l2_len and l3_len fields are related to Tx offloading features. It is undefined in the DPDK API what those fields may contain if an application did not request a Tx offload. Skip reading them if no Tx offloads has been requested. Fixes: 1e728b01120c ("net/iavf: rework Tx path") Cc: stable@dpdk.org Signed-off-by: David Marchand Acked-by: Qi Zhang --- Changes since v1: - updated commitlog and patch to focus on undefined behavior of net/iavf wrt reading l2_len/l3_len, --- drivers/net/iavf/iavf_rxtx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index f7df4665d1..33b0f9f482 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -2643,6 +2643,9 @@ iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1, l2tag1 |= m->vlan_tci; } + if ((m->ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK) == 0) + goto skip_cksum; + /* Set MACLEN */ if (m->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK && !(m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)) @@ -2702,6 +2705,7 @@ iavf_build_data_desc_cmd_offset_fields(volatile uint64_t *qw1, break; } +skip_cksum: *qw1 = rte_cpu_to_le_64((((uint64_t)command << IAVF_TXD_DATA_QW1_CMD_SHIFT) & IAVF_TXD_DATA_QW1_CMD_MASK) | (((uint64_t)offset << IAVF_TXD_DATA_QW1_OFFSET_SHIFT) &