From patchwork Fri Sep 8 11:16:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 131240 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06FC74253D; Fri, 8 Sep 2023 04:58:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A709B402D6; Fri, 8 Sep 2023 04:58:24 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id 1FD4B402BD for ; Fri, 8 Sep 2023 04:58:22 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694141903; x=1725677903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NtD2ePcGBS/hdJGZhKm3HkTeVR3g1CKWsWO+Z4b5sS8=; b=QSkSKEFUQN9pVAC98fPoDL53Xpvz1HAz/yY+/RPeAOEoe+LgCiAEzhbR YPOHWeQnTCE7n3Hmtq8UzeehJKGcGyzrnPWu92N+j0H2s6bg2CD8cMoBa 71Y30wmWb/BnEydatpAXxOXtEvSuIrXSNTNzqoInASMtxgs6ZiLSL8UIN EoABBxInhLg06xIffj9FmQ3okHBrN7ExULVRtWjIz7kKc/KyNpX58E73W c34FSYVWWKk2NwLcxSI3JQ31Ju0RCK/0rfAwQ3ecWg0ZpJlisxoFsV3Qu Y+0Lth81xh553/ZocQYsV13c1dhIvVtrxhSZegR8+mcjIoQSEXrfOfkA9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10826"; a="357002034" X-IronPort-AV: E=Sophos;i="6.02,236,1688454000"; d="scan'208";a="357002034" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2023 19:58:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10826"; a="807789817" X-IronPort-AV: E=Sophos;i="6.02,236,1688454000"; d="scan'208";a="807789817" Received: from dpdk-beileix-icelake.sh.intel.com ([10.67.116.248]) by fmsmga008.fm.intel.com with ESMTP; 07 Sep 2023 19:58:20 -0700 From: beilei.xing@intel.com To: jingjing.wu@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing , Qi Zhang Subject: [PATCH v4 02/10] net/cpfl: introduce interface structure Date: Fri, 8 Sep 2023 11:16:53 +0000 Message-Id: <20230908111701.1022724-3-beilei.xing@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230908111701.1022724-1-beilei.xing@intel.com> References: <20230907151606.849612-1-beilei.xing@intel.com> <20230908111701.1022724-1-beilei.xing@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Beilei Xing Introduce cplf interface structure to distinguish vport and port representor. Signed-off-by: Qi Zhang Signed-off-by: Beilei Xing --- drivers/net/cpfl/cpfl_ethdev.c | 3 +++ drivers/net/cpfl/cpfl_ethdev.h | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index 46b3a52e49..92fe92c00f 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -1803,6 +1803,9 @@ cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params) goto err; } + cpfl_vport->itf.type = CPFL_ITF_TYPE_VPORT; + cpfl_vport->itf.adapter = adapter; + cpfl_vport->itf.data = dev->data; adapter->vports[param->idx] = cpfl_vport; adapter->cur_vports |= RTE_BIT32(param->devarg_id); adapter->cur_vport_nb++; diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index b637bf2e45..53e45035e8 100644 --- a/drivers/net/cpfl/cpfl_ethdev.h +++ b/drivers/net/cpfl/cpfl_ethdev.h @@ -86,7 +86,19 @@ struct p2p_queue_chunks_info { uint32_t rx_buf_qtail_spacing; }; +enum cpfl_itf_type { + CPFL_ITF_TYPE_VPORT, + CPFL_ITF_TYPE_REPRESENTOR +}; + +struct cpfl_itf { + enum cpfl_itf_type type; + struct cpfl_adapter_ext *adapter; + void *data; +}; + struct cpfl_vport { + struct cpfl_itf itf; struct idpf_vport base; struct p2p_queue_chunks_info *p2p_q_chunks_info; @@ -124,5 +136,9 @@ TAILQ_HEAD(cpfl_adapter_list, cpfl_adapter_ext); RTE_DEV_TO_PCI((eth_dev)->device) #define CPFL_ADAPTER_TO_EXT(p) \ container_of((p), struct cpfl_adapter_ext, base) +#define CPFL_DEV_TO_VPORT(dev) \ + ((struct cpfl_vport *)((dev)->data->dev_private)) +#define CPFL_DEV_TO_ITF(dev) \ + ((struct cpfl_itf *)((dev)->data->dev_private)) #endif /* _CPFL_ETHDEV_H_ */