From patchwork Thu Sep 14 12:36:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 131424 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2786442597; Thu, 14 Sep 2023 14:37:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 88FA540DFB; Thu, 14 Sep 2023 14:37:08 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 1E95640A89 for ; Thu, 14 Sep 2023 14:37:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694695026; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SkueaLhjK8bh1TqaDaMiO1JIrUE54z8qpeh1udbLVTQ=; b=Jl0rN4FLnlpq0eL9IRCpTr3zkXnTRyElEUZ6V+1rMDORiTxi4CaXi5tTVQGHBbfV1GuuFb fNnJfESlw1vkrIBbSIUamAwdKnATLUBALar1HOsXNgrScipf6hf3LgtiZyCp/1YUX08g5O qnA9XnAp0+YAM3xZ4kkIEpeTMLJnVKY= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-115-gyX78pouOCuGAnHFYYUjww-1; Thu, 14 Sep 2023 08:37:05 -0400 X-MC-Unique: gyX78pouOCuGAnHFYYUjww-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 7B78F101CC7F; Thu, 14 Sep 2023 12:37:04 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0B63A9A; Thu, 14 Sep 2023 12:37:02 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Abdullah Sevincer , Gaetan Rivet Subject: [PATCH v3 11/15] pci: define some extended capability constants Date: Thu, 14 Sep 2023 14:36:10 +0200 Message-ID: <20230914123615.1705654-12-david.marchand@redhat.com> In-Reply-To: <20230914123615.1705654-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230914123615.1705654-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI extended capability constants and use them in existing drivers. Acked-by: Bruce Richardson Reviewed-by: Chenbo Xia Signed-off-by: David Marchand Acked-by: Abdullah Sevincer --- Changes since v2: - fixed existing SRIOV comment, --- drivers/event/dlb2/pf/dlb2_main.c | 7 ++----- lib/pci/rte_pci.h | 6 ++++-- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 8d960edef6..29e3001627 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -27,9 +27,6 @@ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ -#define DLB2_PCI_EXT_CAP_ID_PRI 0x13 -#define DLB2_PCI_EXT_CAP_ID_ACS 0xD - #define DLB2_PCI_PRI_CTRL_ENABLE 0x1 #define DLB2_PCI_PRI_ALLOC_REQ 0xC #define DLB2_PCI_PRI_CTRL 0x4 @@ -263,7 +260,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) if (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2) slt_word2 = 0; - off = DLB2_PCI_EXT_CAP_ID_PRI; + off = RTE_PCI_EXT_CAP_ID_PRI; pri_cap_offset = rte_pci_find_ext_capability(pdev, off); if (pri_cap_offset >= 0) { @@ -490,7 +487,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } - off = DLB2_PCI_EXT_CAP_ID_ACS; + off = RTE_PCI_EXT_CAP_ID_ACS; acs_cap_offset = rte_pci_find_ext_capability(pdev, off); if (acs_cap_offset >= 0) { diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 00ce390c1c..1fdca91f8b 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -98,9 +98,11 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ -#define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/ +#define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ +#define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ +#define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ -/* Single Root I/O Virtualization */ +/* Single Root I/O Virtualization (RTE_PCI_EXT_CAP_ID_SRIOV) */ #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ #define RTE_PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */