From patchwork Thu Sep 14 12:36:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 131425 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C2A1842597; Thu, 14 Sep 2023 14:37:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 13EAD40698; Thu, 14 Sep 2023 14:37:14 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 4CF0B40293 for ; Thu, 14 Sep 2023 14:37:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694695031; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dnWecOk7oJPCQ35K44kxMGPd6MyqCKOlN7taMjZTSmI=; b=geWDpMnJoDnW7HNcEIuDWv+zW2CJLlY5uuQga58La15TFrPTbBmhXFZpGvIXc38jLgldzc Oc5B+v8222OLZpnbdh9JH9x53icxwMquL62rKeSevzZX+bN+DWHPZj0pdVyr5+7Aw1KgEf +2/1y80SAdsvbbynZlRKgxefrFaoG8w= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-294-_RFElUprMPePwMVDfnFr5g-1; Thu, 14 Sep 2023 08:37:08 -0400 X-MC-Unique: _RFElUprMPePwMVDfnFr5g-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id F1C69800045; Thu, 14 Sep 2023 12:37:07 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id 850F140C6EBF; Thu, 14 Sep 2023 12:37:06 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Abdullah Sevincer , Gaetan Rivet Subject: [PATCH v3 12/15] pci: define some ACS constants Date: Thu, 14 Sep 2023 14:36:11 +0200 Message-ID: <20230914123615.1705654-13-david.marchand@redhat.com> In-Reply-To: <20230914123615.1705654-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230914123615.1705654-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI ACS extended feature constants and use them in existing drivers. Signed-off-by: David Marchand Acked-by: Bruce Richardson Acked-by: Abdullah Sevincer Reviewed-by: Chenbo Xia --- drivers/event/dlb2/pf/dlb2_main.c | 23 ++++++++--------------- lib/pci/rte_pci.h | 9 +++++++++ 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 29e3001627..8e729d1964 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -33,13 +33,6 @@ #define DLB2_PCI_ERR_ROOT_STATUS 0x30 #define DLB2_PCI_ERR_COR_STATUS 0x10 #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 -#define DLB2_PCI_ACS_CAP 0x4 -#define DLB2_PCI_ACS_CTRL 0x6 -#define DLB2_PCI_ACS_SV 0x1 -#define DLB2_PCI_ACS_RR 0x4 -#define DLB2_PCI_ACS_CR 0x8 -#define DLB2_PCI_ACS_UF 0x10 -#define DLB2_PCI_ACS_EC 0x20 static int dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev) @@ -492,16 +485,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) if (acs_cap_offset >= 0) { uint16_t acs_cap, acs_ctrl, acs_mask; - off = acs_cap_offset + DLB2_PCI_ACS_CAP; + off = acs_cap_offset + RTE_PCI_ACS_CAP; if (rte_pci_read_config(pdev, &acs_cap, 2, off) != 2) acs_cap = 0; - off = acs_cap_offset + DLB2_PCI_ACS_CTRL; + off = acs_cap_offset + RTE_PCI_ACS_CTRL; if (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2) acs_ctrl = 0; - acs_mask = DLB2_PCI_ACS_SV | DLB2_PCI_ACS_RR; - acs_mask |= (DLB2_PCI_ACS_CR | DLB2_PCI_ACS_UF); + acs_mask = RTE_PCI_ACS_SV | RTE_PCI_ACS_RR; + acs_mask |= (RTE_PCI_ACS_CR | RTE_PCI_ACS_UF); acs_ctrl |= (acs_cap & acs_mask); ret = rte_pci_write_config(pdev, &acs_ctrl, 2, off); @@ -511,15 +504,15 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = acs_cap_offset + DLB2_PCI_ACS_CTRL; + off = acs_cap_offset + RTE_PCI_ACS_CTRL; if (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2) acs_ctrl = 0; - acs_mask = DLB2_PCI_ACS_RR | DLB2_PCI_ACS_CR; - acs_mask |= DLB2_PCI_ACS_EC; + acs_mask = RTE_PCI_ACS_RR | RTE_PCI_ACS_CR; + acs_mask |= RTE_PCI_ACS_EC; acs_ctrl &= ~acs_mask; - off = acs_cap_offset + DLB2_PCI_ACS_CTRL; + off = acs_cap_offset + RTE_PCI_ACS_CTRL; ret = rte_pci_write_config(pdev, &acs_ctrl, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 1fdca91f8b..a6c52a232d 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -102,6 +102,15 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +/* Access Control Service (RTE_PCI_EXT_CAP_ID_ACS) */ +#define RTE_PCI_ACS_CAP 0x04 /* ACS Capability Register */ +#define RTE_PCI_ACS_CTRL 0x06 /* ACS Control Register */ +#define RTE_PCI_ACS_SV 0x0001 /* Source Validation */ +#define RTE_PCI_ACS_RR 0x0004 /* P2P Request Redirect */ +#define RTE_PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ +#define RTE_PCI_ACS_UF 0x0010 /* Upstream Forwarding */ +#define RTE_PCI_ACS_EC 0x0020 /* P2P Egress Control */ + /* Single Root I/O Virtualization (RTE_PCI_EXT_CAP_ID_SRIOV) */ #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */